Intel S975XBX2 Product Specification - Page 87

Error Messages and Beep Codes Table 44. Port 80h POST Codes POST Code 10 11 12 13 21 22 23 24 25 26 27 28 50 51 52 53 - 57 58 59 5A 5B 5C 5D 70 71 72 78 79 7A Description of POST Operation Host Processor Power-on initialization of the host processor (Boot Strap Processor) Host processor Cache initialization (including APs) Starting Application processor initialization SMM initialization Chipset Initializing a chipset component Memory Reading SPD from memory DIMMs Detecting presence of memory DIMMs Programming timing parameters in the memory controller and the DIMMs Configuring memory Optimizing memory settings Initializing memory, such as ECC init Testing memory PCI Bus Enumerating PCI buses Allocating resources to PCI bus Hot Plug PCI controller initialization Reserved for PCI Bus USB Resetting USB bus Reserved for USB ATA/ATAPI/SATA Resetting PATA/SATA bus and all devices Reserved for ATA SMBus Resetting SMBUS Reserved for SMBUS Local Console Resetting the VGA controller Disabling the VGA controller Enabling the VGA controller Remote Console Resetting the console controller Disabling the console controller Enabling the console controller continued 87