Intel SR1530HCLS Product Specification - Page 51

Intel® Server Systems SR1530CL/SR1530HCL/SR1530HCS and SR1530CLR/SR1530HCLR/SR1530HCLSR Appendix B: POST Code Diagnostic LED Decoder Table 30. Diagnostic LED POST Code Decoder Diagnostic LED Decoder Checkpoint G=Green, R=Red, A=Amber MSB LSB Host Processor 0x10h OFF OFF OFF R 0x11h OFF OFF OFF A 0x12h OFF OFF G R 0x13h OFF OFF G A Chipset 0x21h OFF OFF R G Memory 0x22h OFF OFF A OFF 0x23h OFF OFF A G 0x24h OFF G R OFF 0x25h OFF G R G 0x26h OFF G A OFF 0x27h OFF G A G 0x28h G OFF R OFF PCI Bus 0x50h OFF R OFF R 0x51h OFF R OFF A 0x52h OFF R G R 0x53h OFF R G A 0x54h OFF A OFF R 0x55h OFF A OFF A 0x56h OFF A G R 0x57h OFF A G A USB 0x58h G R OFF R 0x59h G R OFF A ATA/ATAPI/SATA 0x5Ah G R G R 0x5Bh G R G A SMBUS 0x5Ch G A OFF R 0x5Dh G A OFF A Local Console 0x70h OFF R R R 0x71h OFF R R A 0x72h OFF R A R Remote Console 0x78h G R R R 0x79h G R R A 0x7Ah G R A R Description Power-on initialization of the host processor (bootstrap processor) Host processor cache initialization (including AP) Starting application processor initialization SMM initialization Initializing a chipset component Reading configuration data from memory (SPD on DIMM) Detecting presence of memory Programming timing parameters in the memory controller Configuring memory parameters in the memory controller Optimizing memory controller settings Initializing memory, such as ECC init Testing memory Enumerating PCI busses Allocating resources to PCI busses Hot Plug PCI controller initialization Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Reserved for PCI bus Resetting USB bus Reserved for USB devices Resetting PATA/SATA bus and all devices Reserved for ATA Resetting SMBUS Reserved for SMBUS Resetting the video controller (VGA) Disabling the video controller (VGA) Enabling the video controller (VGA) Resetting the console controller Disabling the console controller Enabling the console controller Revision 2.2 43 Intel order number D71005-005