Lenovo PC 300PL Technical Information Manual 6275, 6285 - Page 78

DMA I/O Address Map, of 3. I/O Address Map

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Appendix B. System Address Maps Figure 49 (Page 3 of 3). I/O Address Map Address (Hex) Size 0F40-0F47 8 bytes 0F86-0F87 2 bytes 7000-700D 14 bytes 8000-8037 56 bytes FF00-FF07 8 bytes FFA0-FFA7 8 bytes FFA8-FFAF 8 bytes Description Windows sound system (if present) Available SMBus I/O space registers Power management I/O space registers IDE bus master register Primary bus master IDE registers Secondary bus master IDE registers DMA I/O Address Map The following figure lists resource assignments for the DMA address map. Any addresses that are not shown are reserved. Figure 50 (Page 1 of 2). DMA I/O Address Map Address (Hex) Description 0000 Channel 0, Memory Address register 0001 Channel 0, Transfer Count register 0002 Channel 1, Memory Address register 0003 Channel 1, Transfer Count register 0004 Channel 2, Memory Address register 0005 Channel 2, Transfer Count register 0006 Channel 3, Memory Address register 0007 Channel 3, Transfer Count register 0008 Channels 0-3, Read Status/Write Command register 0009 Channels 0-3, Write Request register 000A Channels 0-3, Write Single Mask register bits 000B Channels 0-3, Mode register (write) 000C Channels 0-3, Clear byte pointer (write) 000D Channels 0-3, Master clear (write)/temp (read) 000E Channels 0-3, Clear Mask register (write) 000F Channels 0-3, Write All Mask register bits 0081 Channel 2, Page Table Address register 3 0082 Channel 3, Page Table Address register 3 0083 Channel 1, Page Table Address register 3 0087 Channel 0, Page Table Address register 3 0089 Channel 6, Page Table Address register 3 008A Channel 7, Page Table Address register 3 008B Channel 5, Page Table Address register 3 008F Channel 4, Page Table Address/Refresh register 00C0 Channel 4, Memory Address register 00C2 Channel 4, Transfer Count register 00C4 Channel 5, Memory Address register 00C6 Channel 5, Transfer Count register Bits 00-15 00-15 00-15 00-15 00-15 00-15 00-15 00-15 00-07 00-02 00-02 00-07 N/A 00-07 00-03 00-03 00-07 00-07 00-07 00-07 00-07 00-07 00-07 00-07 00-15 00-15 00-15 00-15 Byte Pointer Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 66 Technical Information Manual

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Appendix B.
System Address Maps
DMA I/O Address Map
The following figure lists resource assignments for the DMA address map.
Any addresses that are not
shown are reserved.
Figure 49 (Page 3 of 3). I/O Address Map
Address (Hex)
Size
Description
0F40–0F47
8 bytes
Windows sound system (if present)
0F86–0F87
2 bytes
Available
7000–700D
14 bytes
SMBus I/O space registers
8000–8037
56 bytes
Power management I/O space registers
FF00–FF07
8 bytes
IDE bus master register
FFA0–FFA7
8 bytes
Primary bus master IDE registers
FFA8–FFAF
8 bytes
Secondary bus master IDE registers
Figure 50 (Page 1 of 2). DMA I/O Address Map
Address (Hex)
Description
Bits
Byte Pointer
0000
Channel 0, Memory Address register
00–15
Yes
0001
Channel 0, Transfer Count register
00–15
Yes
0002
Channel 1, Memory Address register
00–15
Yes
0003
Channel 1, Transfer Count register
00–15
Yes
0004
Channel 2, Memory Address register
00–15
Yes
0005
Channel 2, Transfer Count register
00–15
Yes
0006
Channel 3, Memory Address register
00–15
Yes
0007
Channel 3, Transfer Count register
00–15
Yes
0008
Channels 0–3, Read Status/Write Command register
00–07
0009
Channels 0–3, Write Request register
00–02
000A
Channels 0–3, Write Single Mask register bits
00–02
000B
Channels 0–3, Mode register (write)
00–07
000C
Channels 0–3, Clear byte pointer (write)
N/A
000D
Channels 0–3, Master clear (write)/temp (read)
00–07
000E
Channels 0–3, Clear Mask register (write)
00–03
000F
Channels 0–3, Write All Mask register bits
00–03
0081
Channel 2, Page Table Address register
3
00–07
0082
Channel 3, Page Table Address register
3
00–07
0083
Channel 1, Page Table Address register
3
00–07
0087
Channel 0, Page Table Address register
3
00–07
0089
Channel 6, Page Table Address register
3
00–07
008A
Channel 7, Page Table Address register
3
00–07
008B
Channel 5, Page Table Address register
3
00–07
008F
Channel 4, Page Table Address/Refresh register
00–07
00C0
Channel 4, Memory Address register
00–15
Yes
00C2
Channel 4, Transfer Count register
00–15
Yes
00C4
Channel 5, Memory Address register
00–15
Yes
00C6
Channel 5, Transfer Count register
00–15
Yes
66
Technical Information Manual