Sony HCD-ZUX9 Service Manual - Page 84

IC901, TMP92CD28AFG-2CB4 USB CONTROLLER USB BOARD, Pin No., Pin Name, Pin Description

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HCD-ZUX9 IC901 TMP92CD28AFG-2CB4 (USB CONTROLLER) (USB BOARD) Pin No. Pin Name I/O Pin Description 1 RESET I Reset signal input from the system controller "L": reset 2 PC0/INT0 I Ready to send signal input from the system controller 3 PC1/INT1 O Not used. Connected to ground. 4 PC2/INT2/TB1IN0 O Not used. Connected to ground. 5 PC3/INT3 I Function selection signal input Fixed at "L" in this set. 6 DVCC3B - Power supply (+3.3 V) 7 PC6/XT1 O Not used. (Open) 8 PC7/XT2 O Not used. (Open) 9 PWE O Not used. (Open) 10 DVSS1B - Ground 11 DVCC1B - Reference voltage input 12 RVOUT1 O Reference voltage output 13, 14 RVIN I Reference voltage (+3.3 V) input 15 RVOUT2 O Reference voltage output 16 DVCC1A - Reference voltage input 17 DVSS1A - Ground 18 to 25 P00/D0 to P07/D7 I/O Two-way data bus with the S-RAM 26 DVSS - Ground 27 DVCC3A - Power supply (+3.3 V) 28 to 35 P10/D8 to P17/D15 I/O Two-way data bus with the S-RAM 36 P40/A0 O Address signal output Not used in this set. (Open) 37 to 43 P41/A1 to P47/A7 O Address signal output to the S-RAM 44 DVSS - Ground 45 DVCC3A - Power supply (+3.3 V) 46 to 54 P50/A8 to P60/A16 O Address signal output to the S-RAM 55 to 58 P61/A17 to P64/A20 O Serial data output to the CD-MP3 processor 59 P65/A21 O Serial data transfer clock signal output to the CD-MP3 processor 60 P66/A22 O Chip enable signal output to the CD-MP3 processor 61 P67/A23 O Not used. (Open) 62 DVSS - Ground 63 DVCC3A - Power supply (+3.3 V) 64 P70/RD O Output enable signal output to the S-RAM 65 P71/SRWR O Write enable signal output to the S-RAM 66 P72/SRLLB O Lower-byte control signal output to the S-RAM 67 P73/SRLUB O Upper-byte control signal output to the S-RAM 68 P74/TA0IN O Not used. (Open) 69 P80/CS0/TA1OUT (BOOT) I Boot mode selection signal input "L": boot mode 70 P82/CS2 I Chip select signal output to the S-RAM 71 P83/CS3/WAIT/TA5OUT O L/R sampling clock signal output to the CD-MP3 processor 72 AM1 I Function mode selection signal input Fixed at "H" in this set. 73 X2 O System clock output (9 MHz) 74 DVSS - Ground 75 X1 I System clock input (9 MHz) 76 DVCC3A - Power supply (+3.3 V) 77 P75/USBOC I Over current detection signal input 78 P76/USBPON O USB VBUS power on/off control signal output "H": power on 79 D+ I/O Two-way data (positive) bus with the USB connector 80 D- I/O Two-way data (negative) bus with the USB connector 81 AM0 I Function mode selection signal input Fixed at "H" in this set. 84

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84
HCD-ZUX9
IC901
TMP92CD28AFG-2CB4 (USB CONTROLLER) (USB BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
RESET
I
Reset signal input from the system controller
“L”: reset
2
PC0/INT0
I
Ready to send signal input from the system controller
3
PC1/INT1
O
Not used.
Connected to ground.
4
PC2/INT2/TB1IN0
O
Not used.
Connected to ground.
5
PC3/INT3
I
Function selection signal input
Fixed at “L” in this set.
6
DVCC3B
—
Power supply (+3.3 V)
7
PC6/XT1
O
Not used. (Open)
8
PC7/XT2
O
Not used. (Open)
9
PWE
O
Not used. (Open)
10
DVSS1B
—
Ground
11
DVCC1B
—
Reference voltage input
12
RVOUT1
O
Reference voltage output
13, 14
RVIN
I
Reference voltage (+3.3 V) input
15
RVOUT2
O
Reference voltage output
16
DVCC1A
—
Reference voltage input
17
DVSS1A
—
Ground
18 to 25
P00/D0 to P07/D7
I/O
Two-way data bus with the S-RAM
26
DVSS
—
Ground
27
DVCC3A
—
Power supply (+3.3 V)
28 to 35
P10/D8 to P17/D15
I/O
Two-way data bus with the S-RAM
36
P40/A0
O
Address signal output
Not used in this set. (Open)
37 to 43
P41/A1 to P47/A7
O
Address signal output to the S-RAM
44
DVSS
—
Ground
45
DVCC3A
—
Power supply (+3.3 V)
46 to 54
P50/A8 to P60/A16
O
Address signal output to the S-RAM
55 to 58
P61/A17 to P64/A20
O
Serial data output to the CD-MP3 processor
59
P65/A21
O
Serial data transfer clock signal output to the CD-MP3 processor
60
P66/A22
O
Chip enable signal output to the CD-MP3 processor
61
P67/A23
O
Not used. (Open)
62
DVSS
—
Ground
63
DVCC3A
—
Power supply (+3.3 V)
64
P70/RD
O
Output enable signal output to the S-RAM
65
P71/SRWR
O
Write enable signal output to the S-RAM
66
P72/SRLLB
O
Lower-byte control signal output to the S-RAM
67
P73/SRLUB
O
Upper-byte control signal output to the S-RAM
68
P74/TA0IN
O
Not used. (Open)
69
P80/CS0/TA1OUT (BOOT)
I
Boot mode selection signal input
“L”: boot mode
70
P82/CS2
I
Chip select signal output to the S-RAM
71
P83/CS3/WAIT/TA5OUT
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input
Fixed at “H” in this set.
73
X2
O
System clock output (9 MHz)
74
DVSS
—
Ground
75
X1
I
System clock input (9 MHz)
76
DVCC3A
—
Power supply (+3.3 V)
77
P75/USBOC
I
Over current detection signal input
78
P76/USBPON
O
USB VBUS power on/off control signal output
“H”: power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D–
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input
Fixed at “H” in this set.