Toshiba Satellite A40 Maintenance Manual - Page 26
Hardware Overview, 2 System Unit Block Diagram - bios password reset
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Page 26 highlights
1 Hardware Overview 1.2 System Unit Block Diagram q PC Card Controller Gate Array • One YEBISU-SS gate array is used. • This gate array has the following functions and components. - PCI interface (PCI Revision2.2) - CardBus/PC Card controller (Yenta2 Version2.2) - SD memory card controller (SDHC Ver.1.2) - SD IO card controller (Ver.1.0) - SmartMedia controller (SMHC Ver.01/SMIL1.0) - SIO (UART) controller (MS Debug Port Specification Ver.1.0) - Docking station interface - Q switch control, reset control - External device interface q BIOS ROM • 8Mbit (Flash memory) − 64KB used for logo − 32KB used for setup and checksum − 128KB used for system BIOS − 64KB used for VGA-BIOS − 64KB used for ACPI − 8KB used for PnP − 8KB used for password security − 16KB used for booting − 128KB are reserved • 5.0V operation • Access time : 120 ns or 90 ns • Data transfer: 8-bit 1-10 Satellite A40 Maintenance Manual (960-458)
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