Intel SAI2 Product Specification - Page 20

Video Modes

Get Intel SAI2 - Ss3/le Dual Fcpga Max-4GB Atx2pci-64 4pci-32 Vid Lan 133mhz PDF manuals and user guides
UPC - 735858149563
View all Intel SAI2 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 20 highlights

SAI2 Server Board Architecture Overview SAI2 Server Board TPS 2.4.2.2.3 Video Modes The Rage XL supports all standard IBM* VGA modes. The following tables show the standard resolutions that this implementation supports, including the number of colors and the refresh rate. Table 3. Standard VGA Modes Resolution 640x480 800x600 1024x768 1280x1024 1600x1200 640x480 800x600 1024x768 640x480 800x600 Refresh Rate (Hz) 100 100 100 72 85 100 100 100 100 100 Colors 256 256 256 256 256 65K 65K 65K 16.7 M 16.7 M 2.4.2.3 CSB5 South Bridge The CSB5 South Bridge is a PCI device that provides multiple PCI functions in a single package: PCI-to-ISA bridge, PCI IDE interface, PCI USB controller, and power management controller. Each function within the CSB5 South Bridge has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller sharing the same PCI bus interface. On the SAI2 baseboard, the primary role of the CSB5 South Bridge is to provide the gateway to all PC-compatible I/O devices and features. The SAI2 server board uses the following CSB5 South Bridge features: • PCI interface • IDE interface • USB interface • PC-compatible timer/counters and Direct Memory Access (DMA) controllers • Baseboard Plug-and-Play support • General purpose I/O • Power management • APIC and 82C59 interrupt controller • Host interface for AT compatible signaling • Internal only ISA bus (no ISA expansion connectors) bridge for communication with Super I/O, and BIOS flash The following sections describe each supported feature as used on the SAI2 server board. 10 Revision 1.0

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
SAI2 Server Board Architecture Overview
SAI2 Server Board TPS
Revision 1.0
10
2.4.2.2.3
Video Modes
The Rage XL supports all standard IBM* VGA modes. The following tables show the standard
resolutions that this implementation supports, including the number of colors and the refresh rate.
Table 3. Standard VGA Modes
Resolution
Refresh Rate (Hz)
Colors
640x480
100
256
800x600
100
256
1024x768
100
256
1280x1024
72
256
1600x1200
85
256
640x480
100
65K
800x600
100
65K
1024x768
100
65K
640x480
100
16.7 M
800x600
100
16.7 M
2.4.2.3
CSB5 South Bridge
The CSB5 South Bridge is a PCI device that provides multiple PCI functions in a single
package: PCI-to-ISA bridge, PCI IDE interface, PCI USB controller, and power management
controller. Each function within the CSB5 South Bridge has its own set of configuration
registers. Once configured, each appears to the system as a distinct hardware controller
sharing the same PCI bus interface.
On the SAI2 baseboard, the primary role of the CSB5 South Bridge is to provide the gateway to
all PC-compatible I/O devices and features. The SAI2 server board uses the following CSB5
South Bridge features:
•
PCI interface
•
IDE interface
•
USB interface
•
PC-compatible timer/counters and Direct Memory Access (DMA) controllers
•
Baseboard Plug-and-Play support
•
General purpose I/O
•
Power management
•
APIC and 82C59 interrupt controller
•
Host interface for AT compatible signaling
•
Internal only ISA bus (no ISA expansion connectors) bridge for communication with
Super I/O, and BIOS flash
The following sections describe each supported feature as used on the SAI2 server board.