Intel SAI2 Product Specification - Page 23

SAI2 Server Board TPS SAI2 Server Board Architecture Overview 2.5.1.5 Real-time Clock The PC87417 contains an MC146818-compatible real-time clock with external battery backup. The device also contains 242 bytes of general purpose battery-backed CMOS RAM. The realtime clock provides system clock and calendar information stored in non-volatile memory. 2.5.1.6 Plug-and-Play Functions / ISA Data Transfers The PC87417 contains all signals for ISA compatible interrupts and DMA channels. This ISA subsystem transfers all SIO peripheral control data to the CSB5 South Bridge as well via the LPC bus interface. The SIO also supports an X-Bus interface that provides control, data and address signals to and from the RAS NVRAM device. 2.5.1.7 Power Management Controller The PC87417 component contains functionality that allows various events to allow the poweron and power-off of the system. This can be from PCI Power Management Events or the front panel. This circuitry is powered from stand-by voltage, which is present anytime the system is plugged into the AC outlet. 2.5.2 BIOS Flash The SAI2 baseboard incorporates an SST39SF040 Flash ROM component. The SST39SF040 is a high-performance 4 megabit memory organized as 512K x8 bits in128 4-KB blocks. The 8-bit flash memory provides 512K x 8 of BIOS and nonvolatile storage space. The flash device is directly addressed as 8-bit ISA memory and accessed through the CSB5 X-Bus interface. 2.5.3 External Device Connectors The external I/O connectors provide support for a PS/2 compatible mouse and keyboard, an SVGA monitor, two serial port connectors, a parallel port connector, a LAN port, and two USB connections. 2.6 Interrupt Routing The SAI2 server board interrupt architecture implements two I/O APICs and two PICs through the use of the integrated components in the CSB5 South Bridge component. The SAI2 server board interrupt architecture allows first and second PCI interrupts to be mapped to compatible interrupts through the PCI Interrupt Address Index Register (I/O Address 0C00h) in the CSB5 South Bridge. The CSB5 South Bridge uses integrated logic to map 16 PCI interrupts to EISA/ISA. In default or Extended APIC configurations, each PCI interrupt can be independently routed to one of the 11 EISA interrupts. The interrupt mapping logic for PCI interrupts is disabled when the make bit in the corresponding I/O APIC redirection table entry is disabled (clear). This interrupt routing mechanism allows a clean transition from PIC mode to an APIC during operating system boot. Revision 1.0 13