Intel SAI2 Product Specification - Page 21

PCI Interface, 4.2.3.2, PCI Bus Master IDE Interface, 4.2.3.3, USB Interface

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SAI2 Server Board TPS SAI2 Server Board Architecture Overview 2.4.2.3.1 PCI Interface The CSB5 South Bridge fully implements a 32-bit PCI master/slave interface, in accordance with Revision 2.2 of the PCI Local Bus Specification. On the SAI2 server board, the PCI interface operates at 33 MHz, using the 5V-signaling environment. 2.4.2.3.2 PCI Bus Master IDE Interface The CSB5 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for intelligent disk drives that have disk controller electronics on-board. The server board includes two IDE connectors, each featuring 40 pins (2 x 20) that support a master and a slave device. The IDE controller provides support for an internally mounted CD-ROM. The IDE controller has the following features: • Programmed Input/Output (PIO) and DMA transfer modes • Up to PIO Mode 4 , DMA Mode 4, and Ultra DMA Mode 5 timings • Transfer rates up to 100 MBps • Buffering for PCI/IDE burst transfers • Master/slave IDE mode • Support for up to two devices per channel 2.4.2.3.3 USB Interface The CSB5 South Bridge contains a USB controller and USB hub. The USB controller moves data between main memory and the two USB connectors provided. The SAI2 server board provides a dual external USB connector interface. Both ports function identically and with the same bandwidth. The external connector is defined by Revision 1.0 of the USB Specification. 2.4.2.4 Compatibility Interrupt Control The CSB5 South Bridge provides the functionality of two 82C59 Programmable Interrupt Controller (PIC) devices, for ISA-compatible interrupt handling. 2.4.2.5 APIC The CSB5 South Bridge integrates a 16-entry I/O APIC that is used to distribute 16 PCI interrupts. It also includes an additional 16-entry I/O APIC for distribution of legacy ISA interrupts. 2.4.2.6 Power Management One of the embedded functions of CSB5 South Bridge is a power management controller. The SAI2 server board uses this to implement ACPI-compliant power management features. SAI2 supports sleep states s0, s1, s4, and s5. Revision 1.0 11

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SAI2 Server Board TPS
SAI2 Server Board Architecture Overview
Revision 1.0
11
2.4.2.3.1
PCI Interface
The CSB5 South Bridge fully implements a 32-bit PCI master/slave interface, in accordance
with Revision 2.2 of the
PCI Local Bus Specification
. On the SAI2 server board, the PCI
interface operates at 33 MHz, using the 5V-signaling environment.
2.4.2.3.2
PCI Bus Master IDE Interface
The CSB5 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for
intelligent disk drives that have disk controller electronics on-board. The server board includes
two IDE connectors, each featuring 40 pins (2 x 20) that support a master and a slave device.
The IDE controller provides support for an internally mounted CD-ROM.
The IDE controller has the following features:
•
Programmed Input/Output (PIO) and DMA transfer modes
•
Up to PIO Mode 4 , DMA Mode 4, and Ultra DMA Mode 5 timings
•
Transfer rates up to 100 MBps
•
Buffering for PCI/IDE burst transfers
•
Master/slave IDE mode
•
Support for up to two devices per channel
2.4.2.3.3
USB Interface
The CSB5 South Bridge contains a USB controller and USB hub. The USB controller moves
data between main memory and the two USB connectors provided.
The SAI2 server board provides a dual external USB connector interface. Both ports function
identically and with the same bandwidth.
The external connector is defined by Revision 1.0 of
the
USB Specification
.
2.4.2.4
Compatibility Interrupt Control
The CSB5 South Bridge provides the functionality of two 82C59 Programmable Interrupt
Controller (PIC) devices, for ISA-compatible interrupt handling.
2.4.2.5
APIC
The CSB5 South Bridge integrates a 16-entry I/O APIC that is used to distribute 16 PCI interrupts.
It also includes an additional 16-entry I/O APIC for distribution of legacy ISA interrupts.
2.4.2.6
Power Management
One of the embedded functions of CSB5 South Bridge is a power management controller. The
SAI2 server board uses this to implement ACPI-compliant power management features. SAI2
supports sleep states s0, s1, s4, and s5.