Intel SAI2 Product Specification - Page 48
Error Messages and Error Codes
UPC - 735858149563
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Basic Input Output System (BIOS) SAI2 Server Board TPS 3.6 Error Messages and Error Codes The system BIOS displays error messages on the video screen. Before video initialization, beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the video monitor. Following are definitions of POST error codes, POST beep codes, and system error messages. 3.6.1 POST Codes After the video adapter has been successfully initialized, the BIOS indicates the current testing phase during POST by writing a 2-digit hex code to I/O location 80h. If a Port-80h card (Postcard*) is installed, it displays this 2-digit code on a pair of hex display LEDs. Table 27. Port-80h Code Definition Code Meaning CP Phoenix* checkpoint (port-80) code The table below contains the port-80 codes displayed during the boot process. A beep code is a series of individual beeps on the PC speaker, each of equal length. The following table describes the error conditions associated with each beep code and the corresponding POST checkpoint code as seen by a 'port 80h' card. For example, if an error occurs at checkpoint 22h, a beep code of 1-3-1-1 is generated. The "-" means there is a pause between the sequence that delimits the sequence. Some POST codes occur before the video display being initialized. To assist in determining the fault, a unique beep-code is derived from these checkpoints as follows: • The 8-bit test point is broken down to four 2-bit groups. • Each group is made one-based (1 through 4) • One to four beeps are generated based on each group's 2-bit pattern. Example: Checkpoint 04Bh will be broken down to: 01 00 10 11 The beep code will be: 2 1 3 4 Table 28. Standard BIOS Port-80 Codes CP Beeps 02 Verify Real Mode Reason 04 Get Processor type 06 Initialize system hardware 08 Initialize chipset registers with initial POST values 09 Set in POST flag 0A Initialize processor registers 0B Enable processor cache 38 Revision 1.0