Sharp FO-2970M Service Manual - Page 38

FO-2970MU [2] Circuit description of control PWB 1. General description Fig. 2 shows the functional blocks of the control PWB, which is composed of 5 blocks. MAIN CONTROL BLOCK MODEM/ CONTROL BLOCK ASIC/PRINTING CONTROL BLOCK 2) M27C800-90F1 (IC14): pin-42 DIP (ROM) EPROM of 8M bit equipped with software for the main CPU. 3) W24010S-70LET (IC1): pin-32 SOP (RAM) Line memory for the main CPU system RAM area and coding/decoding process. Used as the transmission buffer. Memory of recorded data such as daily report and auto dials. When the power is turned off, this memory is backed up by the lithium battery. 4) MSM5118165D (IC11, IC13, IC22): pin-42 SOJ (DRAM) Image memory for recording process. • Memory for recording pixel data at without paper. IMAGE SIGNAL PROCESS BLOCK Fig. 2 Control PWB functional block diagram 2. Description of each block (1) Main control block The main control block is composed of HITACHI CPU (SH2), ROMX1 (8M bit), SRAMX1 (1M bit), DRAMX3 (16M bit). Devices are connected to the bus to control the whole unit. 1) SH7041 (IC5) : pin-144 QFP The CPU Integrated Facsimile Controllers. SH7041, contains an internal 32 bit microprocessor with an external 16 bit address space and dedicated circuitry optimized for facsimile image processing and facsimile machine control and monitoring. PB0/A16 PB1/A17 PB2/IRQ0/POE0/RAS PB3/IRQ1/POE1/CASL PB4/IRQ2/POE2/CASH PB5/IRQ3/POE3/RDWR PB6/IRQ4/A18/BACK PB7/IRQ5/A19/BREQ PB8/IRQ6/A20/WAIT PB9/IRQ7/A21/ADTRG PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PA10/CS0 PA11/CS1 PA12/WRL PA13/WRH PA14/RD PA15/CK PA16/AH PA17/WAIT PA18/BREQ/DRAK0 PA19/BACK/DRAK1 PA20/CASHL PA21/CASHH PA22/WRHL PA23/WRHH PC15/A15 PC14/A14 PC13/A13 PC12/A12 RES/VPP MDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCC PLLCAP PLLVSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS AVREF PROM/MASKROM 128KB/64KB P L , L RAM/CACHE 4KB/1KB DATA TRANSFER CONTROLLER CPU , ,,,,, DIRECT MEMORY ACCESS CONTROLLER INTERRUPT ,
, CONTROLLER USER BREAK BUS STATE CONTROLLER SERIAL COMMUNICATION INTERFACE (X2CHANNELS) COMPARE MATCH TIMER X2CHANNELS) MULTI FUNCTION TIMER PULSE UNIT CONVERTER WATCHDOG TIMER PC11/A11 PC10/A10 PC9/A9 PC8/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD31/D31/ADTRG PD30/D30/IRQOUT PD29/D29/CS3 PD28/D28/CS2 PD27/D27/DAK1 PD26/D26/DACK0 PD25/D25/DREQ1 PD24/D24/DREQ0 PD23/D23/IRQ7 PD22/D22/IRQ6 PD21/D21/IRQ5 PD20/D20/IRQ4 PD19/D19/IRQ3 PD18/D18/IRQ2 PD17/D17/IRQ1 PD16/D16/IRQ0 PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 : PERIPHERAL ADDRESS BUS(32BIT) : PERIPHERAL DATA BUS(16BIT) : INTERNAL ADDRESS BUS(32BIT) : INTERNAL HIGH-ORDER DATA(16BIT) : INTERNAL LOW-ORDER DATA(16BIT) PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C/DACK0/AH PE15/TIOC4D/DACK1/IRQOUT PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF/AN7 Fig. 3 5 - 2