Sharp FO-2970M Service Manual - Page 40

FO-2970MU SH7041 (IC5) Terminal descriptions Classification Code Terminal No. I/O Name Function Data bus D0 ~ D15 (QFP-112) D0 ~ D31 (QFP-144) 45,46 56~60, 62,64~70 72~76,78 80~84 86,88~92 O Data bus Bilateral data bus for 16 bit (Pin plate QFP-112 ) or 32 bit (Pin plate QFP-144). Bus control CS0~CS3 49,50,53 54,56,57 O Chip select 0 to 3 Chip select signals for external memory or device. RD 43 O Read-out Shows reading-out from the external device. WRH 47 O Higher side writing Shows writing in higher 8 bits (bits 15 to 8). WRL 48 O Lower side writing Shows writing in lower 8 bits (bits 7 to 0). WAIT 39,101 I Wait To insert wait cycle into the bus cycle when accessing external space. RAS 31 O Low address strobe Timing signal for low address strobe of DRAM. CASH 34 O Higher column address Timing signal for column address strobe of DRAM. strobe It is output when accessing higher eight bits of data. CASL 32 O Lower column address Timing signal for column address strobe of DRAM. strobe RDWR 36 O DRAM read/write Strobe signal for DRAM writing. AH 2,100 O Address hold Address hold timing signal for the device using multiplex bus of address/data. WRHH 1 (QFP-144) O HH writing Shows writing of bits 31 to 24 of external data. WRHL 3 (QFP-144) O HL writing Shows writing of bits 23 to 16 of external data. CASHH 4 (QFP-144) O HH column address Timing signal for column address strobe of DRAM. strobe It is output when accessing bits 31 to 24 of data. CASHL 29 (QFP-144) O HL column address Timing signal for column address strobe of DRAM. strobe It is output when accessing bits 23 to 16 of data. Multi function timer pulse unit TCLKA TCLKB TCLKC TCLKD 51~54 I MTU timer clock input External clock input terminal for MTU counter. TIOC0A TIOC0B TIOC0C TIOC0D 109~111, 113 I/O MTU input capture/ Channel 0 terminal for inputting Input Capture/outputting Output output conveyer Conveyer/outputting PWM. (Channel 0) TIOC1A TIOC1B 114,115 I/O MTU input capture/ Channel 1 terminal for inputting Input Capture/outputting Output output conveyer Conveyer/outputting PWM. (Channel 1) TIOC2A TIOC1B 116,117 I/O MTU input capture/ Channel 2 terminal for inputting Input Capture/outputting Output output conveyer Conveyer/outputting PWM. (Channel 2) TIOC3A TIOC3B TIOC3C TIOC3D 138~140, I/O MTU input capture/ Channel 3 terminal for inputting Input Capture/outputting Output output conveyer Conveyer/outputting PWM. (Channel 3) TIOC4A TIOC4B TIOC4C TIOC4D 2,5,143,144 I/O MTU input capture/ Channel 4 terminal for inputting Input Capture/outputting Output output conveyer Conveyer/outputting PWM. (Channel 4) Direct memory DREQ0, 60,62,109, I DMA transfer demand Input terminal for external DMA transfer demand. access control DREQ1 111,132,136 (Channels 0 and 1) (DMAC) DRAK0, 2,30,33,110, O DREQ demand Outputs sampling acceptance of external DMA transfer demand DRAK1 113 acceptance (Channels input. 0 and 1) DACK0, DACK1 5,58,59 O DMA transfer strobe Outputs strobe to external I/O of external DMA transfer demand. (Channels 0 and 1) (Continuing) 5 - 4