TEAC DW-224E-V Hardware Specification - Page 16

(Table 14.3-1) IDE Interface signal summary (Sheet 2 of 2) Signal DA0 DA1 DA2 -DMACK DMARQ INTRQ -IOCS16 Description Device address bit 0 Device address bit 1 Device address bit 2 DMA acknowledge DMA request Interupt request Drive 16 bit I/O Direction IN IN IN IN OUT OUT OUT -IOR I/O read IN -HDMARDY DMA ready during Ultra DMA data in bursts IN HSTROBE Data strobe during Ultra DMA data out bursts IN IORDY I/O ready OUT -DDMARDY DMA ready during Ultra DMA data out bursts OUT DSTROBE Data strobe during Ultra DMA data in bursts OUT -DIOW I/O write IN STOP Stop during Ultra DMA data bursts IN -PDIAG -CBLID Passed diagnostics Cable assembly type identifier IN/OUT - -RESET Reset IN 14.4 Interface Timing The following specifications all apply to the signal interface connector terminal of the CD-ROM drive. In timing description, H indicates high level (false) and L low level (true). (1) Reset timing (master/slave) : Fig. 14.4-1 (2) Reset timing (slave) : Fig. 14.4-2 (3) PIO write cycle timing : Fig. 14.4-3 (4) PIO read cycle timing : Fig. 14.4-4 (5) DMA single word transfer timing : Fig. 14.4-5 (6) DMA multi word transfer timing : Fig. 14.4-6 (7) Ultra DMA transfer timing (Data in burst) : Fig. 14.4-7 (8) Ultra DMA transfer timing (Data out burst) : Fig. 14.4-8 - 14 -