TEAC DW-224E-V Hardware Specification - Page 26
Fig.14.4-8 Ultra DMA transfer timing Data out burst Fig. 2 of 3
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Host terminating an Ultra DMA data out burst t74 DMARQ H (device) L t74 -DMACK H (host) L t83 STOP H (host) L t74 −DDMARDY H (device) L HSTROBE H (host) L DD(15:0) H (host) L DA0, DA1, DA2 H (host) L −CS0, −CS1 H (host) L Device terminating an Ultra DMA data t81 t71 t82 t71 t75 t76 CRC t71 t71 DMARQ H (device) L -DMACK H (host) L STOP H (host) L −DDMARDY H (device) L HSTROBE H (host) L DD(15:0) H (host) L DA0, DA1, DA2 H (host) L −CS0, −CS1 H (host) L t74 t80 t74 t81 t71 t82 t81 t71 t75 t76 CRC t71 t71 (Fig.14.4-8) Ultra DMA transfer timing (Data out burst) (Fig. 2 of 3) - 24 -
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° 24 °
(Fig.14.4-8) Ultra DMA transfer timing (Data out burst) (Fig. 2 of 3)
t71
t74
t81
t83
t75
t74
t74
t76
t71
t71
t71
t82
t75
t81
t71
t80
t74
t81
t74
t76
t71
t71
CRC
CRC
t71
t82
Host terminating an Ultra DMA data out burst
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
°DMACK
(host)
STOP
(host)
−
DDMARDY
(device)
H
L
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2
(host)
H
L
−
CS0,
−
CS1
(host)
H
L
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
°DMACK
(host)
STOP
(host)
−
DDMARDY
(device)
H
L
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2
(host)
H
L
−
CS0,
−
CS1
(host)
H
L
Device terminating an Ultra DMA data