Biostar M7VKG M7VKG user's manual - Page 49

AGP Driving Control, AGP Driving Value, AGP Master 1 WS Write, Frame Buffer Size, DRAM Timing By SPD

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Chapter2 BIOS Setup AGP Driving Control By choosing "Auto" the system BIOS will the AGP output Buffer Drive strength P Ctrl by AGP Card. By choosing "Manual", it allows user to set AGP output Buffer Drive strength P Ctrl by manual. The Choices: Auto (default), Manual. AGP Driving Value While AGP driving control item set to "Manual", it allows user to set AGP driving. AGP Master 1 WS Write When Enabled, writes to the AGP(Accelerated Graphics Port) are executed with one wait states. The Choices: Enabled, Disabled (default). AGP Master 1 WS Read When Enabled, read to the AGP(Accelerated Graphics Port) are executed with one wait states. The Choices: Enabled, Disabled (default). Frame Buffer Size This item allows you to set frame butter size. The Choices: 8M (default), 16M, 32M DRAM Timing By SPD This item determines DRAM clock/timing follow SPD or not. The Choices: Enabled, Disabled (default). DRAM Clock This item determines DRAM Clock following the CPU host clock, or 133MHz. The Choices: Host CLK (default), HCLK+33M SDRAM Cycle Length When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer. The Choices: 3 (default), 2. 2-15

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Chapter2
BIOS Setup
2-15
AGP Driving Control
By choosing "Auto" the system BIOS will the AGP output Buffer
Drive strength P Ctrl by AGP Card. By choosing "Manual", it allows
user to set AGP output Buffer Drive strength P Ctrl by manual.
The Choices: Auto
(default), Manual.
AGP Driving Value
While AGP driving control item set to "Manual", it allows user to set
AGP driving.
AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are
executed with one wait states.
The Choices:
Enabled,
Disabled
(default).
AGP Master 1 WS Read
When Enabled, read to the AGP(Accelerated Graphics Port) are
executed with one wait states.
The Choices:
Enabled,
Disabled
(default).
Frame Buffer Size
This item allows you to set frame butter size.
The Choices: 8M
(default), 16M, 32M
DRAM Timing By SPD
This item determines DRAM clock/timing follow SPD or not.
The Choices:
Enabled,
Disabled
(default).
DRAM Clock
This item determines DRAM Clock following the CPU host clock, or 133MHz.
The Choices: Host CLK
(default), HCLK+33M
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
The Choices: 3
(default)
,
2.