Dell S5148F-ON Open Networking Hardware Diagnostic Guide September 2017 - Page 57

Configuration file format

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RMT Control : offset 0x52 = 0x0 7: 4 Undefined = 0 3 RMT Test Enable = 0 2: 0 RMT Test Reboot Count = 0 Status ID Byte : offset 0x53 = 0xe6 POST Control Bits : offset 0x54 = 0x3 7 Force Cold Boot = 0 6 POST Extended Upper DRAM test = 0 5 POST Extended Lower DRAM test = 0 4 POST Extended tests = 0 3 Reserved = 0 2 POST Verbose Mode = 0 1 POST Stop on Error = 1 0 POST Enable = 1 EDA Control Bits : offset 0x55 = 0x3 5: 4 EDA Verbose Level = 0 3 EDA Extended Tests = 0 2 EDA Verbose Mode = 0 1 EDA Stop on Error = 1 0 EDA Enable = 1 EDA Extra Bits : offset 0x56 = 0x0 Control ID Byte : offset 0x57 = 0xea root@dell-diag-os:~# write output ./nvramtool --write --reg=0x54 --val=0x1 Configuration file format The nvramtool configuration file uses the device description format and is the same format as the pltool configuration file. # C - CHIP (Master | Slave - Cpld or FPGA), Address, Name, Access # R - Register, Offset, Mask, Name, RW , Default Val # B - Bit(s), bitnum(s), Name, RW, Default Val # I - Information on the bits ===== C | NVRAM | 0x72 | RTC Extended Memory | io | 0 | - | - | 0x00 | 0x0 R | 0x50 | 8 | 0xFF | Test Status Fail Bits | RO | 0x0 | 0 | 0x0 B | 7 | NVRAM test | RO | 0x0 B | 6 | SSD test | RO | 0x0 B | 5 | COLD/SMF Reg check | RO | 0x0 B | 4 | PCI test | RO | 0x0 B | 3 | Upper DRAM test | RO | 0x0 B | 2 | Lower DRAM test | RO | 0x0 B | 1 | ECC test | RO | 0x0 B | 0 | SPD test | RO | 0x0 R | 0x51 | 8 | 0xFF | Test Status Pass Bits | RO | 0x0 | 0 | 0x0 B | 7 | NVRAM test | RO | 0x0 B | 6 | SSD test | RO | 0x0 B | 5 | CPLD/SMF Reg check | RO | 0x0 B | 4 | PCI test | RO | 0x0 B | 3 | Upper DRAM test | RO | 0x0 B | 2 | Lower DRAM test | RO | 0x0 B | 1 | ECC test | RO | 0x0 Dell EMC DiagOS tools 57

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RMT Control : offset 0x52 = 0x0
7: 4 Undefined = 0
3 RMT Test Enable = 0
2: 0 RMT Test Reboot Count = 0
Status ID Byte : offset 0x53 = 0xe6
POST Control Bits : offset 0x54 = 0x3
7 Force Cold Boot = 0
6 POST Extended Upper DRAM test = 0
5 POST Extended Lower DRAM test = 0
4 POST Extended tests = 0
3 Reserved = 0
2 POST Verbose Mode = 0
1 POST Stop on Error = 1
0 POST Enable = 1
EDA Control Bits : offset 0x55 = 0x3
5: 4 EDA Verbose Level = 0
3 EDA Extended Tests = 0
2 EDA Verbose Mode = 0
1 EDA Stop on Error = 1
0 EDA Enable = 1
EDA Extra Bits : offset 0x56 = 0x0
Control ID Byte : offset 0x57 = 0xea
root@dell-diag-os:~#
write output
./nvramtool --write --reg=0x54 --val=0x1
Configuration
file
format
The
nvramtool
configuration
file
uses the device description format and is the same format as the
pltool
configuration
file.
# C - CHIP (Master | Slave -
Cpld or FPGA), Address, Name, Access
# R - Register, Offset, Mask, Name, RW , Default Val
# B - Bit(s), bitnum(s), Name, RW, Default Val
# I - Information on the bits
=====
C | NVRAM | 0x72 | RTC Extended Memory | io | 0 | - | - | 0x00 | 0x0
R | 0x50 | 8 | 0xFF | Test Status Fail Bits | RO | 0x0 | 0 | 0x0
B |
7
| NVRAM test
| RO | 0x0
B |
6
| SSD test
| RO | 0x0
B |
5
| COLD/SMF Reg check
| RO | 0x0
B |
4
| PCI test
| RO | 0x0
B |
3
| Upper DRAM test
| RO | 0x0
B |
2
| Lower DRAM test
| RO | 0x0
B |
1
| ECC test
| RO | 0x0
B |
0
| SPD test
| RO | 0x0
R | 0x51 | 8 | 0xFF | Test Status Pass Bits | RO | 0x0 | 0 | 0x0
B |
7
| NVRAM test
| RO | 0x0
B |
6
| SSD test
| RO | 0x0
B |
5
| CPLD/SMF Reg check
| RO | 0x0
B |
4
| PCI test
| RO | 0x0
B |
3
| Upper DRAM test
| RO | 0x0
B |
2
| Lower DRAM test
| RO | 0x0
B |
1
| ECC test
| RO | 0x0
Dell EMC DiagOS tools
57