HP Vectra XU 6/XXX HP Vectra XU 6/XXX - Guide to Optimization Performance - Page 39

Higher Clock Speeds, The Pentium Pro Local Bus

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• Shared - the data is valid and copies are stored in the caches of different processors • Invalid - the data is not valid. Data is stored in cache memories as cache lines of 32-bytes. Associated with each cache line are two status bits which define the MESI state of the cache line. Bus Snooping The Pentium Pro processor monitors accesses to memory by other PC devices (including a second processor, if installed) through bus snooping. This involves intercepting the memory addresses issued by other devices and comparing them with the contents of its cache memories. If bus snooping produces a cache hit, the action taken by the processor will depend on the MESI status of the cache line that produced the hit: for modified cache lines the processor will intervene to update the copy held in main memory; for shared or exclusive cache lines, the processor will need to modify the MESI state of the cache line. HIGHER CLOCK SPEEDS The Pentium Pro processor operates at higher internal clock frequencies than any previous x86 family processor. Typically, the Pentium Pro uses an internal clock that is up to three times faster than the clock used for the local bus. This increase in clock speeds has been made possible by superpipeline architecture and the additional functions that the Pentium Pro integrates. With a 256 KB level-two cache memory, the Pentium Pro is able to perform much of its work internally, without needing to access its local bus. THE PENTIUM PRO LOCAL BUS The new features implemented by the Pentium Pro processor are not limited to its internal operation; the Pentium Pro also uses a new protocol for memory accesses performed over its local bus. Previous generation processors in the x86 family used a simple protocol for memory accesses on the local bus; once a bus cycle had been initiated it had to be completed before another access could be begun. As memory accesses require a number of clock cycles to complete, this meant that the local bus would be stalled until the access was complete. Transactional Bus The Pentium Pro supports a transactional local bus, which allows up to eight memory accesses to be outstanding at any one time. Once a memory access has been issued on the local bus, the Pentium Pro can issue other memory accesses while waiting for the first access to complete. By using this transactional protocol, the Pentium Pro processor is able to make better use of its local bus. To use the transactional protocol, the Pentium Pro processor requires support from other devices on the local bus, such as the memory controller. If this support is not available, the Pentium Pro will use the simple protocol, used by previous generation x86 family processors, for memory accesses.

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Shared — the data is valid and copies are stored in the caches of different processors
•
Invalid — the data is not valid.
Data is stored in cache memories as cache lines of 32-bytes. Associated with each cache line
are two status bits which define the MESI state of the cache line.
Bus Snooping
The Pentium Pro processor monitors accesses to memory by other PC devices (including a
second processor, if installed) through bus snooping. This involves intercepting the memory
addresses issued by other devices and comparing them with the contents of its cache
memories.
If bus snooping produces a cache hit, the action taken by the processor will depend on the
MESI status of the cache line that produced the hit: for modified cache lines the processor will
intervene to update the copy held in main memory; for shared or exclusive cache lines, the
processor will need to modify the MESI state of the cache line.
HIGHER CLOCK SPEEDS
The Pentium Pro processor operates at higher internal clock frequencies than any previous x86
family processor. Typically, the Pentium Pro uses an internal clock that is up to three times
faster than the clock used for the local bus.
This increase in clock speeds has been made possible by superpipeline architecture and the
additional functions that the Pentium Pro integrates. With a 256 KB level-two cache memory,
the Pentium Pro is able to perform much of its work internally, without needing to access its
local bus.
THE PENTIUM PRO LOCAL BUS
The new features implemented by the Pentium Pro processor are not limited to its internal
operation; the Pentium Pro also uses a new protocol for memory accesses performed over its
local bus.
Previous generation processors in the x86 family used a simple protocol for memory accesses
on the local bus; once a bus cycle had been initiated it had to be completed before another
access could be begun. As memory accesses require a number of clock cycles to complete,
this meant that the local bus would be stalled until the access was complete.
Transactional Bus
The Pentium Pro supports a transactional local bus, which allows up to eight memory accesses
to be outstanding at any one time. Once a memory access has been issued on the local bus,
the Pentium Pro can issue other memory accesses while waiting for the first access to
complete. By using this transactional protocol, the Pentium Pro processor is able to make
better use of its local bus.
To use the transactional protocol, the Pentium Pro processor requires support from other
devices on the local bus, such as the memory controller. If this support is not available, the
Pentium Pro will use the simple protocol, used by previous generation x86 family processors,
for memory accesses.