HP Vectra XU 6/XXX HP Vectra XU 6/XXX - Guide to Optimization Performance - Page 41

Data Integrity

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With interleaved accesses, the memory controller begins to access the both modules in the pair simultaneously. The time required to access both memory modules is thus less than twice the time required to access a single module. The maximum (peak) data transfer rate that your PC's memory can provide is 267 MB/s. Another advantage of interleaving is that it enables the memory controller to synchronize its activity with accesses made by the processor. The Pentium Pro processor frequently uses burst transfers to read or write entire cache lines in memory. Cache lines are 32 bytes long, which corresponds to four consecutive data transfers of 64 bits each. DATA INTEGRITY Previous generations of PCs protected the integrity of memory data by using parity bits stored with each data byte. Parity is calculated by adding up all the data bits in a byte. If the total is an even number, the parity bit is set to 0, while if the total is an odd number this will be 1. Parity was generated by the PC's memory controller when writing data to memory and this parity would be checked when subsequently reading that data. Any difference between the parity written and that read indicates that one of the bits in the corresponding data byte has changed. The advantage of parity is that it enables the memory controller to detect if memory data has been changed. However, it does not enable the memory controller to correct the error because the precise bit is not identified. Furthermore, if two bits of data are changed within the same byte of data, no error would be detected. ECC Code Your PC uses a different system to guarantee the integrity of your memory data. This system, called Error Correcting Code (ECC), enables the memory controller to detect and automatically correct any single-bit data error that occurs. ECC Code is generated using a mechanism called 8-bit hamming code. This takes larger, disjointed groups of data bits and performs the same addition used for parity to produce an ECC bit. With eight bytes of data, eight ECC bits will be generated, which means that the groups of bits used to generate the ECC bits overlap. The groups of data bits used to calculate the ECC bits are carefully selected, so that a change in any one data bit will change a unique combination of the ECC bits. If a single bit data error occurs, your PC's memory controller decodes the ECC bits to identify exactly which data bit has been changed.

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With interleaved accesses, the memory controller begins to access the both modules in the
pair simultaneously. The time required to access both memory modules is thus less than twice
the time required to access a single module. The maximum (peak) data transfer rate that your
PC’s memory can provide is 267 MB/s.
Another advantage of interleaving is that it enables the memory controller to synchronize its
activity with accesses made by the processor. The Pentium Pro processor frequently uses burst
transfers to read or write entire cache lines in memory. Cache lines are 32 bytes long, which
corresponds to four consecutive data transfers of 64 bits each.
DATA INTEGRITY
Previous generations of PCs protected the integrity of memory data by using parity bits stored
with each data byte. Parity is calculated by adding up all the data bits in a byte. If the total is an
even number, the parity bit is set to 0, while if the total is an odd number this will be 1.
Parity was generated by the PC’s memory controller when writing data to memory and this
parity would be checked when subsequently reading that data. Any difference between the
parity written and that read indicates that one of the bits in the corresponding data byte has
changed.
The advantage of parity is that it enables the memory controller to detect if memory data has
been changed. However, it does not enable the memory controller to correct the error because
the precise bit is not identified. Furthermore, if two bits of data are changed within the same
byte of data, no error would be detected.
ECC Code
Your PC uses a different system to guarantee the integrity of your memory data. This system,
called Error Correcting Code (ECC), enables the memory controller to detect and automatically
correct any single-bit data error that occurs.
ECC Code is generated using a mechanism called 8-bit hamming code. This takes larger,
disjointed groups of data bits and performs the same addition used for parity to produce an
ECC bit. With eight bytes of data, eight ECC bits will be generated, which means that the
groups of bits used to generate the ECC bits overlap.
The groups of data bits used to calculate the ECC bits are carefully selected, so that a change
in any one data bit will change a unique combination of the ECC bits. If a single bit data error
occurs, your PC’s memory controller decodes the ECC bits to identify exactly which data bit
has been changed.