HP Workstation x1000 hp workstation x1000 - technical reference guide - Page 51

MCH overview, accelerated graphics port AGP bus interface

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system board memory controller hub (82845) MCH overview The MCH provides the processor interface, memory interface, AGP interface and hub interface in an Intel 845 chipset platform. The MCH supports a single channel of SDRAM operating in lock-step. It also supports 4x AGP data transfers and 2x/4x AGP fast writes. The primary host interface enhancements include: • Source synchronous double pumped address • Source synchronous quad pumped data • System bus interrupt delivery The MCH supports a 64B cache line size. One processor is supported at a system bus frequency of 100 MHz (400 MHz Data Bus). It supports an AGTL+ host bus with integrated termination supporting 32-bit host addressing. This lets the processor address the entire 4GB space of the MCH's memory address space. The MCH also provides an eight-deep In-Order Queue that supports as many as eight outstanding pipelined address requests on the host bus. Host-initiated I/O signals are subtractively decoded to the hub interface. Host-initiated memory cycles are positively decoded to AGP or SDRAM and are again subtractively decoded to the hub interface. AGP semantic memory accesses initiated from AGP to DRAM are not snooped on the host bus. Memory accesses initiated from AGP using PCI semantics and accesses from the hub interface to DRAM are snooped on the system bus. Memory access whose addresses lie within the AGP aperture are translated using the AGP address translation table, regardless of the originating interface. accelerated graphics port (AGP) bus interface A controller for the AGP 1.5V slot is integrated in the MCH. The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP semantic cycles to the DRAM are not snooped on the host bus. PCI semantic cycles to DRAM are snooped on the host bus. The MCH supports PIPE# or SBA{7.0} AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA{7.0} mechanism must be selected during system initialization. Both upstream and downstream addressing is limited to 32-bit for AGP and AGP/PCI transactions. The MCH contains a 32-deep AGP Requests queue. High priority accesses are supported. All accesses from the AGP interface that fall within the Chapter 2 51

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system board
memory controller hub (82845)
Chapter 2
51
MCH overview
The MCH provides the processor interface, memory interface, AGP
interface and hub interface in an Intel 845 chipset platform. The MCH
supports a single channel of SDRAM operating in lock-step. It also
supports 4x AGP data transfers and 2x/4x AGP fast writes. The primary
host interface enhancements include:
•
Source synchronous double pumped address
•
Source synchronous quad pumped data
•
System bus interrupt delivery
The MCH supports a 64B cache line size. One processor is supported at a
system bus frequency of 100 MHz (400 MHz Data Bus). It supports an
AGTL+ host bus with integrated termination supporting 32-bit host
addressing. This lets the processor address the entire 4GB space of the
MCH’s memory address space. The MCH also provides an eight-deep
In-Order Queue that supports as many as eight outstanding pipelined
address requests on the host bus.
Host-initiated I/O signals are subtractively decoded to the hub interface.
Host-initiated memory cycles are positively decoded to AGP or SDRAM
and are again subtractively decoded to the hub interface.
AGP semantic memory accesses initiated from AGP to DRAM are not
snooped on the host bus. Memory accesses initiated from AGP using PCI
semantics and accesses from the hub interface to DRAM are snooped on
the system bus. Memory access whose addresses lie within the AGP
aperture
are
translated
using
the
AGP
address
translation
table,
regardless of the originating interface.
accelerated graphics port (AGP) bus interface
A controller for the AGP 1.5V slot is integrated in the MCH. The AGP
interface supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP
semantic cycles to the DRAM are not snooped on the host bus. PCI
semantic cycles to DRAM are snooped on the host bus. The MCH
supports PIPE# or SBA{7.0} AGP address mechanisms, but not both
simultaneously. Either the PIPE# or the SBA{7.0} mechanism must be
selected during system initialization. Both upstream and downstream
addressing is limited to 32-bit for AGP and AGP/PCI transactions. The
MCH contains a 32-deep AGP Requests queue. High priority accesses are
supported. All accesses from the AGP interface that fall within the