HP Workstation x1000 hp workstation x1000 - technical reference guide - Page 54

system clocking

Page 54 highlights

system board memory controller hub (82845) system clocking The MCH has the following clock input pins: • Differential BCLK0/BCLK1 for the host interface • 66 MHz clock input for the AGP and hub interface • SDRAM or DDR clocks. Clock synthesizer chip(s) are responsible for generating the system host clocks, AGP and hub interface clocks, PCI clocks and SDRAM clocks. The MCH does not require any relationship between the BCLK host clock and the 66 MHz clock generated for AGP and hub interfaces; they are totally asynchronous from each other. The AGP and hub interfaces run at a constant 66 MHz base frequency. The hub interface runs at 4x. AGP transfers may be 1x/2x/4x. 54 Chapter 2

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system board
memory controller hub (82845)
Chapter 2
54
system clocking
The MCH has the following clock input pins:
Differential BCLK0/BCLK1 for the host interface
66 MHz clock input for the AGP and hub interface
SDRAM or DDR clocks.
Clock synthesizer chip(s) are responsible for generating the system host
clocks, AGP and hub interface clocks, PCI clocks and SDRAM clocks. The
MCH does not require any relationship between the BCLK host clock
and the 66 MHz clock generated for AGP and hub interfaces; they are
totally asynchronous from each other. The AGP and hub interfaces run
at a constant 66 MHz base frequency. The hub interface runs at 4x. AGP
transfers may be 1x/2x/4x.