HP Workstation x1000 hp workstation x1000 - technical reference guide - Page 52

system board memory controller hub (82845) graphic aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and the hub interface are limited to memory writes originating from the hub interface for the AGP bus. The AGP interface is clocked from a dedicated 66 MHz clock. The AGP-to-host/core interface is asynchronous. The AGP buffers operate only in 1.5V mode. They are not 3.3V safe. hub interface The 8-bit hub interface connects the MCH to the ICH2. Most communications between the MCH and the ICH2 occur over this interface. The hub interface runs at 66 MHz/266 MB/s. The hub interface's supported traffic types include: hub interface-to -AGP memory writes, hub interface-to-SDRAM, processor-to-hub interface, messaging (MSI interrupt messages, power management state change, MI, SCI, and SERR error indication). It is assumed that the hub interface is always connected to an ICH2. SDRAM interface The MCH directly supports a single channel of SDRAM memory operating in lock-step. This channel runs at 133MHz and supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM technologies for 8× and 16× devices. These 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAMs use page sizes of 2 KB, 4 KB, 8 KB, and 16 KB. The page size is individually selected for every row. The MCH also provides optional ECC error checking for SDRAM data integrity. During DRAM writes, ECC is generated on a QWord (64-bit) basis. During DRAM reads, and the read of the data that underlies partial writes, the MCH supports detection of single-bit and multiple-bit errors, and will correct single-bit errors when correction is enabled. 52 Chapter 2