Intel BX80571E5300 Data Sheet

Intel BX80571E5300 - Pentium 2.6 GHz Processor Manual

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  • Intel BX80571E5300 | Data Sheet - Page 1
    Intel® Pentium® Dual-Core Processor E5000Δ Series Datasheet December 2008 Document Number: 320467-002
  • Intel BX80571E5300 | Data Sheet - Page 2
    changes to them. The Intel Pentium® dual-core processor E5000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within
  • Intel BX80571E5300 | Data Sheet - Page 3
    Insertion Specifications 38 3.6 Processor Mass Specification 38 3.7 Processor Materials 38 3.8 Processor Markings 38 3.9 Processor Land Coordinates 39 4 Land Listing and Signal Descriptions 41 4.1 Processor Land Assignments 41 4.2 Alphabetical Signals Reference 64 5 Thermal Specifications
  • Intel BX80571E5300 | Data Sheet - Page 4
    89 6.2.8 Enhanced Intel SpeedStep® Technology 90 6.3 Processor Power Status Indicator (PSI) Signal 90 7 Boxed Processor Specifications 91 7.1 Introduction ...91 7.2 Mechanical Specifications 92 7.2.1 Boxed Processor Cooling Solution Dimensions 92 7.2.2 Boxed Processor Fan Heatsink Weight 93
  • Intel BX80571E5300 | Data Sheet - Page 5
    View 92 21 Overall View Space Requirements for the Boxed Processor 93 22 Boxed Processor Fan Heatsink Power Cable Connector Description 94 23 Baseboard Power Header Placement Relative to Processor Socket 95 24 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view 96 25 Boxed
  • Intel BX80571E5300 | Data Sheet - Page 6
    54 24 Signal Description...64 25 Processor Thermal Specifications 76 26 Processor Thermal Profile 77 27 GetTemp0() Error Codes 83 28 Power-On Configuration Option Signals 85 29 Fan Heatsink Power and Signal Specifications 94 30 Fan Heatsink Power and Signal Specifications 98 6 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 7
    to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep® technology, allows tradeoffs to be made between performance and power consumption. The Intel Pentium® dual-core processor E5000 series also includes the Execute Disable Bit capability. This feature
  • Intel BX80571E5300 | Data Sheet - Page 8
    Revision History Revision Number -001 -002 Description • Initial release • Intel® Pentium® dual-core processor E5300 § § Revision Date August 2008 December 2008 8 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 9
    ® Pentium® dual-core processor E5000 series are 64-bit processors that maintain compatibility with IA-32 software. In this document, the Intel® Pentium® dual-core processor E5000 series may be referred to as "the processor." In this document, unless otherwise specified, the Intel® Pentium® dual-core
  • Intel BX80571E5300 | Data Sheet - Page 10
    clarification: • Intel® Pentium® dual-core processor E5000 series - Dual core processor in the FC-LGA8 package with a 2 MB L2 cache. • Processor - For this document, the term processor is the generic form of the Intel® Pentium® dual-core processor E5000 series. • Voltage Regulator Design Guide - For
  • Intel BX80571E5300 | Data Sheet - Page 11
    Intel® Pentium® Dual-Core Processor E5000 Series Thermal and Mechanical Design Guidelines Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket LGA775 Socket Mechanical Design Guide Intel® 64 and IA-32 Intel Architecture Software Developer's Manuals
  • Intel BX80571E5300 | Data Sheet - Page 12
    Introduction 12 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 13
    act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4. Failure to do so can result in timing violations or reduced lifetime
  • Intel BX80571E5300 | Data Sheet - Page 14
    VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel® Pentium® dual-core Processor E5000 Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the
  • Intel BX80571E5300 | Data Sheet - Page 15
    Electrical Specifications Table 2. Voltage Identification Definition VID VID VID VID VID VID VID VID 76543210 Voltage 00000000 OFF 00000010 1.6 0 0 0 0 0 1 0 0 1.5875 0 0 0 0 0 1 1 0 1.575 0 0 0 0 1 0 0 0 1.5625 00001010 1.55 0 0 0 0 1 1 0 0 1.5375 0 0 0 0 1 1 1 0 1.525 0 0 0 1 0 0 0
  • Intel BX80571E5300 | Data Sheet - Page 16
    Specifications 2.4 2.5 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors motherboard supporting
  • Intel BX80571E5300 | Data Sheet - Page 17
    Core voltage with respect to VSS -0.3 VTT FSB termination voltage with respect to VSS -0.3 TCASE Processor case temperature See Section 5 TSTORAGE Processor For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2.
  • Intel BX80571E5300 | Data Sheet - Page 18
    2.6.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes2, 10 VID Range VID 0.8500 - 1.3625 V 1 Core VCC Processor Number (2 MB Cache): E5200 E5300 VCC for 775_VR_CONFIG_06: 2.50 GHz 2.66 GHz Refer to
  • Intel BX80571E5300 | Data Sheet - Page 19
    to the Voltage Regulator Design Guide to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. 10. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. Processor VCC Static and
  • Intel BX80571E5300 | Data Sheet - Page 20
    processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details. VCC Overshoot The processor specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands. VCC Overshoot Specifications
  • Intel BX80571E5300 | Data Sheet - Page 21
    is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the
  • Intel BX80571E5300 | Data Sheet - Page 22
    Electrical Specifications 2.7.1 Table 7. FSB Signal Groups The front side bus signals have to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the
  • Intel BX80571E5300 | Data Sheet - Page 23
    Drain signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. Datasheet 23
  • Intel BX80571E5300 | Data Sheet - Page 24
    Table 11. Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. GTL+ Signal Group DC Specifications Symbol Parameter Min
  • Intel BX80571E5300 | Data Sheet - Page 25
    mV. Platform Environment Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed
  • Intel BX80571E5300 | Data Sheet - Page 26
    for the system host. Extended trace lengths might appear as additional nodes. GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination
  • Intel BX80571E5300 | Data Sheet - Page 27
    are to VSS. 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor's core frequency is a multiple of the
  • Intel BX80571E5300 | Data Sheet - Page 28
    Specifications Table 15. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency 1/6 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10 1/10.5 1/11 1/11.5 1/12 1/12.5 1/13 1/13.5 1/14 1/15 Core select the frequency of the processor input clock (BCLK[1:0]). Table
  • Intel BX80571E5300 | Data Sheet - Page 29
    An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 4 for DC specifications. 2.8.4 BCLK[1:0] Specifications Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ VL Input Low Voltage -0.30
  • Intel BX80571E5300 | Data Sheet - Page 30
    : BCLK[1:0] Rise and Fall Slew Rate 2.5 - 8 V/nS 3 5 T6: Slew Rate Matching N/A N/A 20 % 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 200 MHz BCLK[1:0]. 2. Duty Cycle (High time/Period) must be between 40 and 60
  • Intel BX80571E5300 | Data Sheet - Page 31
    Electrical Specifications Figure 4. Measurement Points for Differential Clock Waveforms +150 mV 0.0 V -150 mV Diff Slew_rise V_swing Slew _fall T5 = BCLK[1:0] rise and fall time through the swing region +150 mV 0.0V - 150 mV § § Datasheet 31
  • Intel BX80571E5300 | Data Sheet - Page 32
    Electrical Specifications 32 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 33
    Package Mechanical Specifications 3 Package Mechanical Specifications Figure 5. The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An
  • Intel BX80571E5300 | Data Sheet - Page 34
    Figure 6. Processor Package Drawing Sheet 1 of 3 Package Mechanical Specifications 34 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 35
    Package Mechanical Specifications Figure 7. Processor Package Drawing Sheet 2 of 3 Datasheet 35
  • Intel BX80571E5300 | Data Sheet - Page 36
    Figure 8. Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications 36 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 37
    maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits
  • Intel BX80571E5300 | Data Sheet - Page 38
    Design Guide. 3.6 Processor Mass Specification The typical mass of the processor Processor Markings Figure 9 shows the topside markings on the processor. This diagram is to aid in the identification of the processor. Processor Top-Side Markings Example INTEL ©M'06 E5200 Intel® Pentium® Dual-Core
  • Intel BX80571E5300 | Data Sheet - Page 39
    Package Mechanical Specifications 3.9 Processor Land Coordinates . Figure 10. Figure 10 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants, Top View V CC / V SS 30
  • Intel BX80571E5300 | Data Sheet - Page 40
    Package Mechanical Specifications 40 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 41
    and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 11 and Figure 12. These
  • Intel BX80571E5300 | Data Sheet - Page 42
    Land Listing and Signal Descriptions Figure 11. land-out Diagram (Top View - Left Side) 30 29 28 AN VCC VCC VSS 27 VSS 26 VCC 25 VCC 24 VSS 23 VSS 22 VCC 21 VCC 20 VSS 19 VCC 18 VCC 17 VSS 16 VSS 15 VCC AM VCC VCC VSS AL VCC VCC VSS AK VSS VSS VSS AJ VSS VSS VSS AH VCC VCC
  • Intel BX80571E5300 | Data Sheet - Page 43
    Land Listing and Signal Descriptions Figure 12. land-out Diagram (Top View - Right Side) 14 VCC VCC VCC VCC VCC VCC VCC VCC VCC 13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS VSS
  • Intel BX80571E5300 | Data Sheet - Page 44
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction A3# A4# A5# A6# A7# L5 Source Synch Input/Output P6 Source Synch Input/Output M5 Source Synch Input/Output L4 Source Synch Input/Output M4 Source Synch Input/Output A8
  • Intel BX80571E5300 | Data Sheet - Page 45
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55#
  • Intel BX80571E5300 | Data Sheet - Page 46
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction FC31 FC32 FC33 FC34 FC35 J16 H15 H16 J17 H4 Power/Other Power/Other Power/Other Power/Other Power/Other FC36 FC37 FC38 FC39 FC40 FC41 FERR#/PBE# GTLREF0 GTLREF1 HIT#
  • Intel BX80571E5300 | Data Sheet - Page 47
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC E3
  • Intel BX80571E5300 | Data Sheet - Page 48
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC AJ18 AJ19 AJ21 AJ22 AJ25 Power/Other Power/Other Power/Other Power/Other Power/Other VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel BX80571E5300 | Data Sheet - Page 49
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC J28 J29 J30
  • Intel BX80571E5300 | Data Sheet - Page 50
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VID0 VID1 VID2 VID3 VID4 AM2 Asynch CMOS AL5 Asynch CMOS AM3 Asynch CMOS AL6 Asynch CMOS AK4 Asynch CMOS Output Output Output Output Output VID5 VID6 VID7 VRDSEL VSS
  • Intel BX80571E5300 | Data Sheet - Page 51
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AF30 Power/
  • Intel BX80571E5300 | Data Sheet - Page 52
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS AN24 Power/Other AN27 Power/Other AN28 Power/Other C10 Power/Other C13 Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel BX80571E5300 | Data Sheet - Page 53
    Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N6 N7 P23
  • Intel BX80571E5300 | Data Sheet - Page 54
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction A2 VSS Power/Other A3 RS2# Common Clock Input A4 D02# Source Synch Input/Output A5 D04# Source Synch Input/Output A6 VSS Power/Other A7 D07# Source Synch
  • Intel BX80571E5300 | Data Sheet - Page 55
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 DBI3# Source Synch Input/
  • Intel BX80571E5300 | Data Sheet - Page 56
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output
  • Intel BX80571E5300 | Data Sheet - Page 57
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction H29 FC15 Power/Other H30 BSEL1 Asynch CMOS Output J1 VTT_OUT_LE FT Power/Other Output J2 FC3 Power/Other J3 FC22 Power/Other J4 VSS Power/Other J5 REQ1#
  • Intel BX80571E5300 | Data Sheet - Page 58
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction M29 M30 N1 N2 N3 VCC VCC PWRGOOD IGNNE# VSS Power/Other Power/Other Power/Other Asynch CMOS Power/Other Input Input N4 RESERVED N5 RESERVED N6 VSS Power/Other N7 VSS
  • Intel BX80571E5300 | Data Sheet - Page 59
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction U27 VCC Power/Other U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other V1 MSID1 Power/Other Output V2 RESERVED V3 VSS Power/Other V4 A15# Source
  • Intel BX80571E5300 | Data Sheet - Page 60
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AB24 AB25 AB26 AB27 AB28 VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Power/Other Power/Other AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC23 AC24 AC25 AC26 AC27
  • Intel BX80571E5300 | Data Sheet - Page 61
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16
  • Intel BX80571E5300 | Data Sheet - Page 62
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AH28 AH29 AH30 AJ1 AJ2 VCC VCC VCC BPM1# BPM0# Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input/Output AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11
  • Intel BX80571E5300 | Data Sheet - Page 63
    Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AM1 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM20 AM21 AM22
  • Intel BX80571E5300 | Data Sheet - Page 64
    asserted, the processor masks physical address bit 20 (A20 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction 64 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 65
    are completed, then releases the bus by de-asserting BPRI#. Input/ Output BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination
  • Intel BX80571E5300 | Data Sheet - Page 66
    64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may
  • Intel BX80571E5300 | Data Sheet - Page 67
    state, requires chipset support and may not be available on all platforms. NOTE: Some processors may not have the Deep Sleep State enabled, refer to the Specification Update for specific proceswor and stepping guidance. Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data
  • Intel BX80571E5300 | Data Sheet - Page 68
    event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[1:0] determine the
  • Intel BX80571E5300 | Data Sheet - Page 69
    with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these processor FSB throughout the bus locked operation and ensure the atomicity of lock. Output On the processor these signals are connected on the package to Vss. As an alternative to MSID, Intel
  • Intel BX80571E5300 | Data Sheet - Page 70
    REQ[4:0]# RESET# RESERVED RS[2:0]# SKTOCC# Input PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. 'Clean' implies that the signal will remain low (capable of sinking
  • Intel BX80571E5300 | Data Sheet - Page 71
    SLP# pin, and corresponding low power state, requires chipset support and may not be available on all platforms. NOTE: Some processors may not have the Sleep State enabled, refer to the Specification Update for specific processor and stepping guidance. Input SMI# (System Management Interrupt) is
  • Intel BX80571E5300 | Data Sheet - Page 72
    de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid). Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools
  • Intel BX80571E5300 | Data Sheet - Page 73
    , the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable
  • Intel BX80571E5300 | Data Sheet - Page 74
    Land Listing and Signal Descriptions 74 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 75
    allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power
  • Intel BX80571E5300 | Data Sheet - Page 76
    to remain within specification. Table 25. Processor Thermal Specifications Processor Number Core Frequency (GHz) Thermal Design Power (W)3,4 Extended HALT Power (W)1 Deeper Sleep Power (W)2 E5200 2.50 65.0 8 6 E5300 2.66 65.0 8 4 775_VR_ CONFIG_06 Guidance5 Minimum TC (°C) Maximum
  • Intel BX80571E5300 | Data Sheet - Page 77
    Thermal Specifications and Design Considerations Table 26. Processor Thermal Profile Power (W) 0 2 4 6 8 10 12 14 16 18 57.5 58.4 59.3 60.2 61.1 62.0 62.9 63.8 64.7 65.6 Figure 13. Processor Series Thermal Profile Power 48 50 52 54 56 58 60 62 64 65 Maximum Tc (°C) 66.5 67.4 68.3 69.2 70.1 71
  • Intel BX80571E5300 | Data Sheet - Page 78
    14. The maximum and minimum case temperatures (TC) for the processor is specified in Table 25. This temperature specification is meant to help ensure proper operation of the processor. Figure 14 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on
  • Intel BX80571E5300 | Data Sheet - Page 79
    drivers, or interrupt handling routines. Thermal Monitor 2 The processor also supports specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor
  • Intel BX80571E5300 | Data Sheet - Page 80
    Thermal Specifications and Design Considerations Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering T stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same
  • Intel BX80571E5300 | Data Sheet - Page 81
    the processor remains within specification. If the processor enters Design Guide for processor core voltage (VCC) must be removed within the timeframe defined in Table 10. Platform Environment Control Interface (PECI) Introduction PECI offers an interface for thermal monitoring of Intel processor
  • Intel BX80571E5300 | Data Sheet - Page 82
    . TCC activates at a PECI count of zero. Conceptual Fan Control Diagram on PECI-Based Platforms 5.3.2 5.3.2.1 5.3.2.2 PECI Specifications PECI Device Address The PECI register resides at address 30h. PECI Command Support PECI command support is covered in detail in the Platform Environment Control
  • Intel BX80571E5300 | Data Sheet - Page 83
    is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can fault condition. PECI GetTemp0() Error Code Support The error codes supported for the processor GetTemp() command are listed in Table 27
  • Intel BX80571E5300 | Data Sheet - Page 84
    Thermal Specifications and Design Considerations 84 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 85
    asserted during RESET#. 3. Disabling of any of the cores within the processors must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the processor package. 6.2 Clock Control and Low Power States The
  • Intel BX80571E5300 | Data Sheet - Page 86
    power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The halted core will transition to the Normal state
  • Intel BX80571E5300 | Data Sheet - Page 87
    one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT powerdown state must be enabled via the BIOS for the processor to remain within its specification. The processor will automatically
  • Intel BX80571E5300 | Data Sheet - Page 88
    HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced the processor will return to the Extended HALT state or Extended Stop Grant state. Sleep the processor is not in these states is out of specification and may result in unapproved operation. In the Sleep state, the processor is
  • Intel BX80571E5300 | Data Sheet - Page 89
    pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is reduced to a lower level. The Deeper Sleep state is
  • Intel BX80571E5300 | Data Sheet - Page 90
    core frequency is changed. In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Voltage/Frequency selection is software controlled by writing to processor MSR's (Model Specific
  • Intel BX80571E5300 | Data Sheet - Page 91
    of a boxed processor. Note: Figure 18. Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions your local Intel Sales Representative for this document. Mechanical Representation of the Boxed Processor NOTE: The airflow of the fan heatsink is
  • Intel BX80571E5300 | Data Sheet - Page 92
    This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 18 shows a mechanical representation of the boxed processor. Figure 19. Clearance is required around the fan heatsink to ensure unimpeded airflow
  • Intel BX80571E5300 | Data Sheet - Page 93
    pinout are shown in Figure 22. Baseboards must provide a matched power header to support the boxed processor. Table 29 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses at
  • Intel BX80571E5300 | Data Sheet - Page 94
    Boxed Processor Specifications Figure 22. The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The
  • Intel BX80571E5300 | Data Sheet - Page 95
    system, and ultimately the responsibility of the system integrator. The processor temperature specification is provided in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 25) in chassis that provide good thermal management
  • Intel BX80571E5300 | Data Sheet - Page 96
    Boxed Processor Specifications Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 96 Datasheet
  • Intel BX80571E5300 | Data Sheet - Page 97
    . Figure 26. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to Table 29 for the specific requirements. Boxed Processor Fan Heatsink Set Points Increasing Fan Speed & Noise Higher
  • Intel BX80571E5300 | Data Sheet - Page 98
    the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 29) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise. Intel
  • Intel BX80571E5300 | Data Sheet - Page 99
    logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Intel Pentium® dual-core processor E5000 series systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature
  • Intel BX80571E5300 | Data Sheet - Page 100
    Debug Tools Specifications 100 Datasheet
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Document Number: 320467-002
Intel
®
Pentium
®
Dual-Core
Processor E5000
Δ
Series
Datasheet
December 2008