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Intel BX80571E5300 Data Sheet - Page 46

Land Name, Signal Buffer, Direction

UPC - 735858204996

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Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction FC31 FC32 FC33 FC34 FC35 J16 H15 H16 J17 H4 Power/Other Power/Other Power/Other Power/Other Power/Other FC36 FC37 FC38 FC39 FC40 FC41 FERR#/PBE# GTLREF0 GTLREF1 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LOCK# MSID0 MSID1 PECI PROCHOT# PSI# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED AD3 Power/Other AB3 Power/Other G10 Power/Other AA2 Power/Other AM6 Power/Other C9 Power/Other R3 Asynch CMOS Output H1 Power/Other Input H2 Power/Other Input D4 Common Clock Input/Output E4 Common Clock Input/Output AB2 Asynch CMOS Output N2 Asynch CMOS Input P3 Asynch CMOS Input AK3 TAP Input AJ3 TAP Input K1 Asynch CMOS Input L1 Asynch CMOS Input C3 Common Clock Input/Output W1 Power/Other Output V1 Power/Other Output G5 Power/Other Input/Output AL2 Asynch CMOS Input/Output Y3 Asynch CMOS Output N1 Power/Other Input K4 Source Synch Input/Output J5 Source Synch Input/Output M6 Source Synch Input/Output K6 Source Synch Input/Output J6 Source Synch Input/Output V2 A20 AC4 AE4 Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction RESERVED RESERVED RESERVED RESERVED RESERVED AE6 AH2 D1 D14 D16 RESERVED E23 RESERVED E6 RESERVED E7 RESERVED F23 RESERVED F29 RESERVED G6 RESERVED N4 RESERVED N5 RESERVED P5 RESET# G23 Common Clock RS0# B3 Common Clock RS1# F5 Common Clock RS2# A3 Common Clock SKTOCC# AE8 Power/Other SLP# L2 Asynch CMOS SMI# P2 Asynch CMOS STPCLK# M3 Asynch CMOS TCK AE1 TAP TDI AD1 TAP TDO AF1 TAP TESTHI0 F26 Power/Other TESTHI1 W3 Power/Other TESTHI10 H5 Power/Other TESTHI12/ FC44 W2 Power/Other TESTHI2 F25 Power/Other TESTHI3 G25 Power/Other TESTHI4 G27 Power/Other TESTHI5 G26 Power/Other TESTHI6 G24 Power/Other TESTHI7 F24 Power/Other TESTHI8/FC42 G3 Power/Other TESTHI9/FC43 G4 Power/Other THERMTRIP# M2 Asynch CMOS TMS AC1 TAP Input Input Input Input Output Input Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input Input Output Input 46 Datasheet

Section	Page
Intel® Pentium® Dual-Core Processor E5000D Series	1
Contents	3
Figures	5
Tables	6
Intel® Pentium® Dual-Core Processor E5000 Series Features	7
Revision History	8
1 Introduction	9
1.1 Terminology	9
1.1.1 Processor Terminology Definitions	10
1.2 References	11
Table 1. References	11
2 Electrical Specifications	13
2.1 Power and Ground Lands	13
2.2 Decoupling Guidelines	13
2.2.1 VCC Decoupling	13
2.2.2 VTT Decoupling	13
2.2.3 FSB Decoupling	14
2.3 Voltage Identification	14
Table 2. Voltage Identification Definition	15
2.4 Reserved, Unused, and TESTHI Signals	16
2.5 Power Segment Identifier (PSID)	16
2.6 Voltage and Current Specification	17
2.6.1 Absolute Maximum and Minimum Ratings	17
Table 3. Absolute Maximum and Minimum Ratings	17
2.6.2 DC Voltage and Current Specification	18
Table 4. Voltage and Current Specifications	18
Table 5. Processor VCC Static and Transient Tolerance	19
Figure 1. Processor VCC Static and Transient Tolerance	20
2.6.3 VCC Overshoot	20
Table 6. VCC Overshoot Specifications	20
Figure 2. VCC Overshoot Example Waveform	21
2.6.4 Die Voltage Validation	21
2.7 Signaling Specifications	21
2.7.1 FSB Signal Groups	22
Table 7. FSB Signal Groups	22
Table 8. Signal Characteristics	23
Table 9. Signal Reference Voltages	23
2.7.2 CMOS and Open Drain Signals	23
2.7.3 Processor DC Specifications	24
Table 10. GTL+ Signal Group DC Specifications	24
Table 11. Open Drain and TAP Output Signal Group DC Specifications	24
Table 12. CMOS Signal Group DC Specifications	25
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	25
Table 13. PECI DC Electrical Limits	26
2.7.3.2 GTL+ Front Side Bus Specifications	26
Table 14. GTL+ Bus Voltage Definitions	27
2.8 Clock Specifications	27
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	27
Table 15. Core Frequency to FSB Multiplier Configuration	28
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	28
Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]	29
2.8.3 Phase Lock Loop (PLL) and Filter	29
2.8.4 BCLK[1:0] Specifications	29
Table 17. Front Side Bus Differential BCLK Specifications	29
Table 18. FSB Differential Clock Specifications (800 MHz FSB)	30
Figure 3. Differential Clock Waveform	30
Figure 4. Measurement Points for Differential Clock Waveforms	31
3 Package Mechanical Specifications	33
Figure 5. Processor Package Assembly Sketch	33
3.1 Package Mechanical Drawing	33
Figure 6. Processor Package Drawing Sheet 1 of 3	34
Figure 7. Processor Package Drawing Sheet 2 of 3	35
Figure 8. Processor Package Drawing Sheet 3 of 3	36
3.2 Processor Component Keep-Out Zones	37
3.3 Package Loading Specifications	37
Table 19. Processor Loading Specifications	37
3.4 Package Handling Guidelines	37
Table 20. Package Handling Guidelines	37
3.5 Package Insertion Specifications	38
3.6 Processor Mass Specification	38
3.7 Processor Materials	38
Table 21. Processor Materials	38
3.8 Processor Markings	38
Figure 9. Processor Top-Side Markings Example	38
3.9 Processor Land Coordinates	39
Figure 10. Processor Land Coordinates and Quadrants, Top View	39
4 Land Listing and Signal Descriptions	41
4.1 Processor Land Assignments	41
Figure 11. land-out Diagram (Top View - Left Side)	42
Figure 12. land-out Diagram (Top View - Right Side)	43
Table 22. Alphabetical Land Assignments	44
Table 23. Numerical Land Assignment	54
4.2 Alphabetical Signals Reference	64
Table 24. Signal Description (Sheet 10 of 10)	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
Table 25. Processor Thermal Specifications	76
Table 26. Processor Thermal Profile	77
Figure 13. Processor Series Thermal Profile	77
5.1.2 Thermal Metrology	78
Figure 14. Case Temperature (TC) Measurement Location	78
5.2 Processor Thermal Features	78
5.2.1 Thermal Monitor	78
5.2.2 Thermal Monitor 2	79
Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering	80
5.2.3 On-Demand Mode	80
5.2.4 PROCHOT# Signal	80
5.2.5 THERMTRIP# Signal	81
5.3 Platform Environment Control Interface (PECI)	81
5.3.1 Introduction	81
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	82
Figure 16. Conceptual Fan Control Diagram on PECI-Based Platforms	82
5.3.2 PECI Specifications	82
5.3.2.1 PECI Device Address	82
5.3.2.2 PECI Command Support	82
5.3.2.3 PECI Fault Handling Requirements	83
5.3.2.4 PECI GetTemp0() Error Code Support	83
Table 27. GetTemp0() Error Codes	83
6 Features	85
6.1 Power-On Configuration Options	85
Table 28. Power-On Configuration Option Signals	85
6.2 Clock Control and Low Power States	85
Figure 17. Processor Low Power State Machine	86
6.2.1 Normal State	86
6.2.2 HALT and Extended HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Extended HALT Powerdown State	87
6.2.3 Stop Grant and Extended Stop Grant States	87
6.2.3.1 Stop-Grant State	87
6.2.3.2 Extended Stop Grant State	88
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	88
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	88
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	88
6.2.5 Sleep State	88
6.2.6 Deep Sleep State	89
6.2.7 Deeper Sleep State	89
6.2.8 Enhanced Intel SpeedStep® Technology	90
6.3 Processor Power Status Indicator (PSI) Signal	90
7 Boxed Processor Specifications	91
7.1 Introduction	91
Figure 18. Mechanical Representation of the Boxed Processor	91
7.2 Mechanical Specifications	92
7.2.1 Boxed Processor Cooling Solution Dimensions	92
Figure 19. Space Requirements for the Boxed Processor (Side View)	92
Figure 20. Space Requirements for the Boxed Processor (Top View)	92
Figure 21. Overall View Space Requirements for the Boxed Processor	93
7.2.2 Boxed Processor Fan Heatsink Weight	93
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	93
7.3 Electrical Requirements	93
7.3.1 Fan Heatsink Power Supply	93
Figure 22. Boxed Processor Fan Heatsink Power Cable Connector Description	94
Table 29. Fan Heatsink Power and Signal Specifications	94
Figure 23. Baseboard Power Header Placement Relative to Processor Socket	95
7.4 Thermal Specifications	95
7.4.1 Boxed Processor Cooling Requirements	95
Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)	96
Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)	96
7.4.2 Variable Speed Fan	97
Figure 26. Boxed Processor Fan Heatsink Set Points	97
Table 30. Fan Heatsink Power and Signal Specifications	98
8 Debug Tools Specifications	99
8.1 Logic Analyzer Interface (LAI)	99
8.1.1 Mechanical Considerations	99

Match case Limit results 1 per page

Land Listing and Signal Descriptions

Datasheet

FC31

J16

Power/Other

FC32

H15

Power/Other

FC33

H16

Power/Other

FC34

J17

Power/Other

FC35

Power/Other

FC36

AD3

Power/Other

FC37

AB3

Power/Other

FC38

G10

Power/Other

FC39

AA2

Power/Other

FC40

AM6

Power/Other

FC41

Power/Other

FERR#/PBE#

Asynch CMOS

Output

GTLREF0

Power/Other

Input

GTLREF1

Power/Other

Input

HIT#

Common Clock

Input/Output

HITM#

Common Clock

Input/Output

IERR#

AB2

Asynch CMOS

Output

IGNNE#

Asynch CMOS

Input

INIT#

Asynch CMOS

Input

ITP_CLK0

AK3

TAP

Input

ITP_CLK1

AJ3

TAP

Input

LINT0

Asynch CMOS

Input

LINT1

Asynch CMOS

Input

LOCK#

Common Clock

Input/Output

MSID0

Power/Other

Output

MSID1

Power/Other

Output

PECI

Power/Other

Input/Output

PROCHOT#

AL2

Asynch CMOS

Input/Output

PSI#

Asynch CMOS

Output

PWRGOOD

Power/Other

Input

REQ0#

Source Synch

Input/Output

REQ1#

Source Synch

Input/Output

REQ2#

Source Synch

Input/Output

REQ3#

Source Synch

Input/Output

REQ4#

Source Synch

Input/Output

RESERVED

A20

RESERVED

AC4

RESERVED

AE4

Table 22.

Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Type

Direction

RESERVED

AE6

RESERVED

AH2

RESERVED

D14

RESERVED

D16

RESERVED

E23

RESERVED

F23

RESERVED

F29

RESERVED

RESET#

G23

Common Clock

Input

RS0#

Common Clock

Input

RS1#

Common Clock

Input

RS2#

Common Clock

Input

SKTOCC#

AE8

Power/Other

Output

SLP#

Asynch CMOS

Input

SMI#

Asynch CMOS

Input

STPCLK#

Asynch CMOS

Input

TCK

AE1

TAP

Input

TDI

AD1

TAP

Input

TDO

AF1

TAP

Output

TESTHI0

F26

Power/Other

Input

TESTHI1

Power/Other

Input

TESTHI10

Power/Other

Input

TESTHI12/

FC44

Power/Other

Input

TESTHI2

F25

Power/Other

Input

TESTHI3

G25

Power/Other

Input

TESTHI4

G27

Power/Other

Input

TESTHI5

G26

Power/Other

Input

TESTHI6

G24

Power/Other

Input

TESTHI7

F24

Power/Other

Input

TESTHI8/FC42

Power/Other

Input

TESTHI9/FC43

Power/Other

Input

THERMTRIP#

Asynch CMOS

Output

TMS

AC1

TAP

Input

Table 22.

Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Type

Direction