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Intel BX80571E5300 Data Sheet - Page 18

DC Voltage and Current Specification - e5300

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Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes2, 10 VID Range VID 0.8500 - 1.3625 V 1 Core VCC Processor Number (2 MB Cache): E5200 E5300 VCC for 775_VR_CONFIG_06: 2.50 GHz 2.66 GHz Refer to Table 5, Figure 1 V 3, 4, 5 VCC_BOOT VCCPLL ICC Default VCC voltage for initial power up PLL VCC Processor Number (2 MB Cache): VCC for 775_VR_CONFIG_06: E5200 2.50 GHz E5300 2.66 GHz - - 5% - 1.10 1.50 - + 5% - 75 75 V V A6 FSB termination voltage on Intel 3 series Chipset family boards 1.045 1.1 1.155 VTT (DC + AC specifications) on Intel 4 series Chipset family boards 1.14 V 7, 8 1.2 1.26 VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT ICC_VCCPLL ICC_GTLREF DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per land ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable ICC for PLL land ICC for GTLREF - - 580 mA 4.5 - - A9 4.6 - - 130 mA - - 200 µA NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® technology, or Extended HALT State). 2. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. 4. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. 5. Refer to Table 5 and Figure 1, for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. 6. ICC_MAX specification is based on VCC_MAX loadline. Refer to Figure 1 for details. 18 Datasheet

Section	Page
Intel® Pentium® Dual-Core Processor E5000D Series	1
Contents	3
Figures	5
Tables	6
Intel® Pentium® Dual-Core Processor E5000 Series Features	7
Revision History	8
1 Introduction	9
1.1 Terminology	9
1.1.1 Processor Terminology Definitions	10
1.2 References	11
Table 1. References	11
2 Electrical Specifications	13
2.1 Power and Ground Lands	13
2.2 Decoupling Guidelines	13
2.2.1 VCC Decoupling	13
2.2.2 VTT Decoupling	13
2.2.3 FSB Decoupling	14
2.3 Voltage Identification	14
Table 2. Voltage Identification Definition	15
2.4 Reserved, Unused, and TESTHI Signals	16
2.5 Power Segment Identifier (PSID)	16
2.6 Voltage and Current Specification	17
2.6.1 Absolute Maximum and Minimum Ratings	17
Table 3. Absolute Maximum and Minimum Ratings	17
2.6.2 DC Voltage and Current Specification	18
Table 4. Voltage and Current Specifications	18
Table 5. Processor VCC Static and Transient Tolerance	19
Figure 1. Processor VCC Static and Transient Tolerance	20
2.6.3 VCC Overshoot	20
Table 6. VCC Overshoot Specifications	20
Figure 2. VCC Overshoot Example Waveform	21
2.6.4 Die Voltage Validation	21
2.7 Signaling Specifications	21
2.7.1 FSB Signal Groups	22
Table 7. FSB Signal Groups	22
Table 8. Signal Characteristics	23
Table 9. Signal Reference Voltages	23
2.7.2 CMOS and Open Drain Signals	23
2.7.3 Processor DC Specifications	24
Table 10. GTL+ Signal Group DC Specifications	24
Table 11. Open Drain and TAP Output Signal Group DC Specifications	24
Table 12. CMOS Signal Group DC Specifications	25
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	25
Table 13. PECI DC Electrical Limits	26
2.7.3.2 GTL+ Front Side Bus Specifications	26
Table 14. GTL+ Bus Voltage Definitions	27
2.8 Clock Specifications	27
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	27
Table 15. Core Frequency to FSB Multiplier Configuration	28
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	28
Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]	29
2.8.3 Phase Lock Loop (PLL) and Filter	29
2.8.4 BCLK[1:0] Specifications	29
Table 17. Front Side Bus Differential BCLK Specifications	29
Table 18. FSB Differential Clock Specifications (800 MHz FSB)	30
Figure 3. Differential Clock Waveform	30
Figure 4. Measurement Points for Differential Clock Waveforms	31
3 Package Mechanical Specifications	33
Figure 5. Processor Package Assembly Sketch	33
3.1 Package Mechanical Drawing	33
Figure 6. Processor Package Drawing Sheet 1 of 3	34
Figure 7. Processor Package Drawing Sheet 2 of 3	35
Figure 8. Processor Package Drawing Sheet 3 of 3	36
3.2 Processor Component Keep-Out Zones	37
3.3 Package Loading Specifications	37
Table 19. Processor Loading Specifications	37
3.4 Package Handling Guidelines	37
Table 20. Package Handling Guidelines	37
3.5 Package Insertion Specifications	38
3.6 Processor Mass Specification	38
3.7 Processor Materials	38
Table 21. Processor Materials	38
3.8 Processor Markings	38
Figure 9. Processor Top-Side Markings Example	38
3.9 Processor Land Coordinates	39
Figure 10. Processor Land Coordinates and Quadrants, Top View	39
4 Land Listing and Signal Descriptions	41
4.1 Processor Land Assignments	41
Figure 11. land-out Diagram (Top View - Left Side)	42
Figure 12. land-out Diagram (Top View - Right Side)	43
Table 22. Alphabetical Land Assignments	44
Table 23. Numerical Land Assignment	54
4.2 Alphabetical Signals Reference	64
Table 24. Signal Description (Sheet 10 of 10)	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
Table 25. Processor Thermal Specifications	76
Table 26. Processor Thermal Profile	77
Figure 13. Processor Series Thermal Profile	77
5.1.2 Thermal Metrology	78
Figure 14. Case Temperature (TC) Measurement Location	78
5.2 Processor Thermal Features	78
5.2.1 Thermal Monitor	78
5.2.2 Thermal Monitor 2	79
Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering	80
5.2.3 On-Demand Mode	80
5.2.4 PROCHOT# Signal	80
5.2.5 THERMTRIP# Signal	81
5.3 Platform Environment Control Interface (PECI)	81
5.3.1 Introduction	81
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	82
Figure 16. Conceptual Fan Control Diagram on PECI-Based Platforms	82
5.3.2 PECI Specifications	82
5.3.2.1 PECI Device Address	82
5.3.2.2 PECI Command Support	82
5.3.2.3 PECI Fault Handling Requirements	83
5.3.2.4 PECI GetTemp0() Error Code Support	83
Table 27. GetTemp0() Error Codes	83
6 Features	85
6.1 Power-On Configuration Options	85
Table 28. Power-On Configuration Option Signals	85
6.2 Clock Control and Low Power States	85
Figure 17. Processor Low Power State Machine	86
6.2.1 Normal State	86
6.2.2 HALT and Extended HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Extended HALT Powerdown State	87
6.2.3 Stop Grant and Extended Stop Grant States	87
6.2.3.1 Stop-Grant State	87
6.2.3.2 Extended Stop Grant State	88
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	88
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	88
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	88
6.2.5 Sleep State	88
6.2.6 Deep Sleep State	89
6.2.7 Deeper Sleep State	89
6.2.8 Enhanced Intel SpeedStep® Technology	90
6.3 Processor Power Status Indicator (PSI) Signal	90
7 Boxed Processor Specifications	91
7.1 Introduction	91
Figure 18. Mechanical Representation of the Boxed Processor	91
7.2 Mechanical Specifications	92
7.2.1 Boxed Processor Cooling Solution Dimensions	92
Figure 19. Space Requirements for the Boxed Processor (Side View)	92
Figure 20. Space Requirements for the Boxed Processor (Top View)	92
Figure 21. Overall View Space Requirements for the Boxed Processor	93
7.2.2 Boxed Processor Fan Heatsink Weight	93
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	93
7.3 Electrical Requirements	93
7.3.1 Fan Heatsink Power Supply	93
Figure 22. Boxed Processor Fan Heatsink Power Cable Connector Description	94
Table 29. Fan Heatsink Power and Signal Specifications	94
Figure 23. Baseboard Power Header Placement Relative to Processor Socket	95
7.4 Thermal Specifications	95
7.4.1 Boxed Processor Cooling Requirements	95
Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)	96
Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)	96
7.4.2 Variable Speed Fan	97
Figure 26. Boxed Processor Fan Heatsink Set Points	97
Table 30. Fan Heatsink Power and Signal Specifications	98
8 Debug Tools Specifications	99
8.1 Logic Analyzer Interface (LAI)	99
8.1.1 Mechanical Considerations	99

Match case Limit results 1 per page

Electrical Specifications

Datasheet

2.6.2

DC Voltage and Current Specification

NOTES:

Each processor is programmed with a maximum valid voltage identification value (VID),

which is set at manufacturing and can not be altered. Individual maximum VID values are

calibrated during manufacturing such that two processors at the same frequency may have

different settings within the VID range. Note that this differs from the VID employed by the

processor during a power management event (Thermal Monitor 2, Enhanced Intel

SpeedStep

technology, or Extended HALT State).

Unless otherwise noted, all specifications in this table are based on estimates and

simulations or empirical data. These specifications will be updated with characterized data

from silicon measurements at a later date.

These voltages are targets only. A variable voltage source should exist on systems in the

event that a different voltage is required. See

Section 2.3

and

Table 2

for more

information.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE

lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe

capacitance, and 1 M

minimum impedance. The maximum length of ground wire on the

probe should be less than 5 mm. Ensure external noise from the system is not coupled into

the oscilloscope probe.

Refer to

Table 5

and

Figure 1

, for the minimum, typical, and maximum V

allowed for a

given current. The processor should not be subjected to any V

and I

combination

wherein V

exceeds V

CC_MAX

for a given current.

CC_MAX

specification is based on V

CC_

MAX

loadline. Refer to

Figure 1

for details.

Table 4.

Voltage and Current Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

2, 10

VID Range

VID

0.8500

—

1.3625

Core V

Processor Number

(2 MB Cache):

E5200

E5300

for

775_VR_CONFIG_06:

2.50 GHz

2.66 GHz

Refer to

Table 5

Figure 1

3, 4, 5

CC_BOOT

Default V

voltage for initial power up

—

1.10

—

CCPLL

PLL V

- 5%

1.50

+ 5%

Processor Number

(2 MB Cache):

E5200

E5300

for

775_VR_CONFIG_06:

2.50 GHz

2.66 GHz

—

FSB termination

voltage

(DC + AC

specifications)

on Intel 3 series

Chipset family boards

1.045

1.1

1.155

7, 8

on Intel 4 series

Chipset family boards

1.14

1.2

1.26

VTT_OUT_LEFT

and

VTT_OUT_RIGHT

DC Current that may be drawn from

VTT_OUT_LEFT and VTT_OUT_RIGHT per

land

—

580

for V

supply before V

stable

for V

supply after V

stable

—

4.5

4.6

CC_VCCPLL

for PLL land

—

130

CC_GTLREF

for GTLREF

—

200

μA