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Intel BX80571E5300 Data Sheet - Page 56

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UPC - 735858204996

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Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 VSS Power/Other D37# Source Synch Input/Output D38# Source Synch Input/Output VSS Power/Other D41# Source Synch Input/Output D43# Source Synch Input/Output VSS Power/Other RESERVED TESTHI7 Power/Other Input TESTHI2 Power/Other Input TESTHI0 Power/Other Input VTT_SEL Power/Other Output BCLK0 Clock Input RESERVED FC27 Power/Other COMP2 Power/Other Input TESTHI8/ FC42 Power/Other Input TESTHI9/ FC43 Power/Other Input PECI Power/Other Input/Output RESERVED DEFER# Common Clock Input BPRI# Common Clock Input D16# Source Synch Input/Output FC38 Power/Other DBI1# Source Synch Input/Output DSTBN1# Source Synch Input/Output D27# Source Synch Input/Output D29# Source Synch Input/Output D31# Source Synch Input/Output D32# Source Synch Input/Output D36# Source Synch Input/Output D35# Source Synch Input/Output DSTBP2# Source Synch Input/Output Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction G20 G21 G22 G23 G24 DSTBN2# D44# D47# RESET# TESTHI6 Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Input Power/Other Input G25 G26 G27 G28 G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 TESTHI3 TESTHI5 TESTHI4 BCLK1 BSEL0 BSEL2 GTLREF0 GTLREF1 VSS FC35 TESTHI10 VSS VSS VSS VSS VSS VSS VSS VSS VSS FC32 FC33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Clock Asynch CMOS Asynch CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input Output Output Input Input Input 56 Datasheet

Section	Page
Intel® Pentium® Dual-Core Processor E5000D Series	1
Contents	3
Figures	5
Tables	6
Intel® Pentium® Dual-Core Processor E5000 Series Features	7
Revision History	8
1 Introduction	9
1.1 Terminology	9
1.1.1 Processor Terminology Definitions	10
1.2 References	11
Table 1. References	11
2 Electrical Specifications	13
2.1 Power and Ground Lands	13
2.2 Decoupling Guidelines	13
2.2.1 VCC Decoupling	13
2.2.2 VTT Decoupling	13
2.2.3 FSB Decoupling	14
2.3 Voltage Identification	14
Table 2. Voltage Identification Definition	15
2.4 Reserved, Unused, and TESTHI Signals	16
2.5 Power Segment Identifier (PSID)	16
2.6 Voltage and Current Specification	17
2.6.1 Absolute Maximum and Minimum Ratings	17
Table 3. Absolute Maximum and Minimum Ratings	17
2.6.2 DC Voltage and Current Specification	18
Table 4. Voltage and Current Specifications	18
Table 5. Processor VCC Static and Transient Tolerance	19
Figure 1. Processor VCC Static and Transient Tolerance	20
2.6.3 VCC Overshoot	20
Table 6. VCC Overshoot Specifications	20
Figure 2. VCC Overshoot Example Waveform	21
2.6.4 Die Voltage Validation	21
2.7 Signaling Specifications	21
2.7.1 FSB Signal Groups	22
Table 7. FSB Signal Groups	22
Table 8. Signal Characteristics	23
Table 9. Signal Reference Voltages	23
2.7.2 CMOS and Open Drain Signals	23
2.7.3 Processor DC Specifications	24
Table 10. GTL+ Signal Group DC Specifications	24
Table 11. Open Drain and TAP Output Signal Group DC Specifications	24
Table 12. CMOS Signal Group DC Specifications	25
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	25
Table 13. PECI DC Electrical Limits	26
2.7.3.2 GTL+ Front Side Bus Specifications	26
Table 14. GTL+ Bus Voltage Definitions	27
2.8 Clock Specifications	27
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	27
Table 15. Core Frequency to FSB Multiplier Configuration	28
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	28
Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]	29
2.8.3 Phase Lock Loop (PLL) and Filter	29
2.8.4 BCLK[1:0] Specifications	29
Table 17. Front Side Bus Differential BCLK Specifications	29
Table 18. FSB Differential Clock Specifications (800 MHz FSB)	30
Figure 3. Differential Clock Waveform	30
Figure 4. Measurement Points for Differential Clock Waveforms	31
3 Package Mechanical Specifications	33
Figure 5. Processor Package Assembly Sketch	33
3.1 Package Mechanical Drawing	33
Figure 6. Processor Package Drawing Sheet 1 of 3	34
Figure 7. Processor Package Drawing Sheet 2 of 3	35
Figure 8. Processor Package Drawing Sheet 3 of 3	36
3.2 Processor Component Keep-Out Zones	37
3.3 Package Loading Specifications	37
Table 19. Processor Loading Specifications	37
3.4 Package Handling Guidelines	37
Table 20. Package Handling Guidelines	37
3.5 Package Insertion Specifications	38
3.6 Processor Mass Specification	38
3.7 Processor Materials	38
Table 21. Processor Materials	38
3.8 Processor Markings	38
Figure 9. Processor Top-Side Markings Example	38
3.9 Processor Land Coordinates	39
Figure 10. Processor Land Coordinates and Quadrants, Top View	39
4 Land Listing and Signal Descriptions	41
4.1 Processor Land Assignments	41
Figure 11. land-out Diagram (Top View - Left Side)	42
Figure 12. land-out Diagram (Top View - Right Side)	43
Table 22. Alphabetical Land Assignments	44
Table 23. Numerical Land Assignment	54
4.2 Alphabetical Signals Reference	64
Table 24. Signal Description (Sheet 10 of 10)	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
Table 25. Processor Thermal Specifications	76
Table 26. Processor Thermal Profile	77
Figure 13. Processor Series Thermal Profile	77
5.1.2 Thermal Metrology	78
Figure 14. Case Temperature (TC) Measurement Location	78
5.2 Processor Thermal Features	78
5.2.1 Thermal Monitor	78
5.2.2 Thermal Monitor 2	79
Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering	80
5.2.3 On-Demand Mode	80
5.2.4 PROCHOT# Signal	80
5.2.5 THERMTRIP# Signal	81
5.3 Platform Environment Control Interface (PECI)	81
5.3.1 Introduction	81
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	82
Figure 16. Conceptual Fan Control Diagram on PECI-Based Platforms	82
5.3.2 PECI Specifications	82
5.3.2.1 PECI Device Address	82
5.3.2.2 PECI Command Support	82
5.3.2.3 PECI Fault Handling Requirements	83
5.3.2.4 PECI GetTemp0() Error Code Support	83
Table 27. GetTemp0() Error Codes	83
6 Features	85
6.1 Power-On Configuration Options	85
Table 28. Power-On Configuration Option Signals	85
6.2 Clock Control and Low Power States	85
Figure 17. Processor Low Power State Machine	86
6.2.1 Normal State	86
6.2.2 HALT and Extended HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Extended HALT Powerdown State	87
6.2.3 Stop Grant and Extended Stop Grant States	87
6.2.3.1 Stop-Grant State	87
6.2.3.2 Extended Stop Grant State	88
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	88
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	88
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	88
6.2.5 Sleep State	88
6.2.6 Deep Sleep State	89
6.2.7 Deeper Sleep State	89
6.2.8 Enhanced Intel SpeedStep® Technology	90
6.3 Processor Power Status Indicator (PSI) Signal	90
7 Boxed Processor Specifications	91
7.1 Introduction	91
Figure 18. Mechanical Representation of the Boxed Processor	91
7.2 Mechanical Specifications	92
7.2.1 Boxed Processor Cooling Solution Dimensions	92
Figure 19. Space Requirements for the Boxed Processor (Side View)	92
Figure 20. Space Requirements for the Boxed Processor (Top View)	92
Figure 21. Overall View Space Requirements for the Boxed Processor	93
7.2.2 Boxed Processor Fan Heatsink Weight	93
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	93
7.3 Electrical Requirements	93
7.3.1 Fan Heatsink Power Supply	93
Figure 22. Boxed Processor Fan Heatsink Power Cable Connector Description	94
Table 29. Fan Heatsink Power and Signal Specifications	94
Figure 23. Baseboard Power Header Placement Relative to Processor Socket	95
7.4 Thermal Specifications	95
7.4.1 Boxed Processor Cooling Requirements	95
Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)	96
Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)	96
7.4.2 Variable Speed Fan	97
Figure 26. Boxed Processor Fan Heatsink Set Points	97
Table 30. Fan Heatsink Power and Signal Specifications	98
8 Debug Tools Specifications	99
8.1 Logic Analyzer Interface (LAI)	99
8.1.1 Mechanical Considerations	99

Match case Limit results 1 per page

Land Listing and Signal Descriptions

Datasheet

F11

D23#

Source Synch

Input/Output

F12

D24#

Source Synch

Input/Output

F13

VSS

Power/Other

F14

D28#

Source Synch

Input/Output

F15

D30#

Source Synch

Input/Output

F16

VSS

Power/Other

F17

D37#

Source Synch

Input/Output

F18

D38#

Source Synch

Input/Output

F19

VSS

Power/Other

F20

D41#

Source Synch

Input/Output

F21

D43#

Source Synch

Input/Output

F22

VSS

Power/Other

F23

RESERVED

F24

TESTHI7

Power/Other

Input

F25

TESTHI2

Power/Other

Input

F26

TESTHI0

Power/Other

Input

F27

VTT_SEL

Power/Other

Output

F28

BCLK0

Clock

Input

F29

RESERVED

FC27

Power/Other

COMP2

Power/Other

Input

TESTHI8/

FC42

Power/Other

Input

TESTHI9/

FC43

Power/Other

Input

PECI

Power/Other

Input/Output

RESERVED

DEFER#

Common Clock

Input

BPRI#

Common Clock

Input

D16#

Source Synch

Input/Output

G10

FC38

Power/Other

G11

DBI1#

Source Synch

Input/Output

G12

DSTBN1#

Source Synch

Input/Output

G13

D27#

Source Synch

Input/Output

G14

D29#

Source Synch

Input/Output

G15

D31#

Source Synch

Input/Output

G16

D32#

Source Synch

Input/Output

G17

D36#

Source Synch

Input/Output

G18

D35#

Source Synch

Input/Output

G19

DSTBP2#

Source Synch

Input/Output

Table 23.

Numerical Land

Assignment

Land #

Land Name

Signal Buffer

Type

Direction

G20

DSTBN2#

Source Synch

Input/Output

G21

D44#

Source Synch

Input/Output

G22

D47#

Source Synch

Input/Output

G23

RESET#

Common Clock

Input

G24

TESTHI6

Power/Other

Input

G25

TESTHI3

Power/Other

Input

G26

TESTHI5

Power/Other

Input

G27

TESTHI4

Power/Other

Input

G28

BCLK1

Clock

Input

G29

BSEL0

Asynch CMOS

Output

G30

BSEL2

Asynch CMOS

Output

GTLREF0

Power/Other

Input

GTLREF1

Power/Other

Input

VSS

Power/Other

FC35

Power/Other

TESTHI10

Power/Other

Input

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

H10

VSS

Power/Other

H11

VSS

Power/Other

H12

VSS

Power/Other

H13

VSS

Power/Other

H14

VSS

Power/Other

H15

FC32

Power/Other

H16

FC33

Power/Other

H17

VSS

Power/Other

H18

VSS

Power/Other

H19

VSS

Power/Other

H20

VSS

Power/Other

H21

VSS

Power/Other

H22

VSS

Power/Other

H23

VSS

Power/Other

H24

VSS

Power/Other

H25

VSS

Power/Other

H26

VSS

Power/Other

H27

VSS

Power/Other

H28

VSS

Power/Other

Table 23.

Numerical Land

Assignment

Land #

Land Name

Signal Buffer

Type

Direction