Acer AT350 F1 User Manual - Page 69

Lockstep mode, 1B and 2B memory should be the same type, size

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57 Dual processors configuration CPU 1 CPU 2 Config 1C 1B 1A 2C 2B 2A 3C 3B 3A 1C 1B 1A 2C 2B 2A 3C 3B 3A A X X NA NA NA NA NA NA B X X NA NA NA X X NA NA NA C X X X X NA NA NA X X NA NA NA D X X X X NA NA NA X X X X NA NA NA E X X X X X X NA NA NA X X X X NA NA NA F X X X X X X NA NA NA X X X X X X NA NA NA Notes: 1. Place DIMMs in "X" location. 2. DIMM population must correspond to the above tables. 3. DIMM modules support 1 GB, 2 GB and 4 GB DIMMs. 4. DIMM modules support 8 GB and 16 GB DIMMs (support depends on availability). 5. Do not mix UDIMMs with RDIMMs. 6. 3-DIMM per channel configuration is only available for single/dual rank RDIMM. Lockstep mode • In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 1 and Channel 2. This is done to support SDDC for DRAM devices with 8-bit wide data ports. The same address is used on both channels such that an address error on any channel is detectable by ECC. Lockstep Channel mode is the only RAS mode that supports x8 SDDC. • Channel 3 has no function and cannot be populated in this mode. • Follow the population rules described in independent mode. • DIMM modules installed in channels 1 and 2 must be identical - 1A and 2A should be the same type, size and manufacturer. 1B and 2B memory should be the same type, size and manufacturer. However, it is not necessary for slot A to have the same memory module as slot B within a channel. • The same rule applies to processor 2.

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57
Dual processors configuration
Notes:
1. Place DIMMs in “X” location.
2. DIMM population must correspond to the above tables.
3. DIMM modules support 1 GB, 2 GB and 4 GB DIMMs.
4. DIMM modules support 8 GB and 16 GB DIMMs (support
depends on availability).
5. Do not mix UDIMMs with RDIMMs.
6. 3-DIMM per channel configuration is only available for
single/dual rank RDIMM.
Lockstep mode
In Lockstep Channel Mode, each memory access is a 128-bit data
access that spans Channel 1 and Channel 2. This is done to support
SDDC for DRAM devices with 8-bit wide data ports. The same
address is used on both channels such that an address error on any
channel is detectable by ECC. Lockstep Channel mode is the only
RAS mode that supports x8 SDDC.
Channel 3 has no function and cannot be populated in this mode.
Follow the population rules described in independent mode.
DIMM modules installed in channels 1 and 2 must be identical —
1A and 2A should be the same type, size and manufacturer.
1B and 2B memory should be the same type, size and
manufacturer. However, it is not necessary for slot A to have the
same memory module as slot B within a channel.
The same rule applies to processor 2.
CPU 1
CPU 2
Config
1C
1B
1A
2C
2B
2A
3C
3B
3A
1C
1B
1A
2C
2B
2A
3C
3B
3A
A
X
X
NA
NA
NA
NA
NA
NA
B
X
X
NA
NA
NA
X
X
NA
NA
NA
C
X
X
X
X
NA
NA
NA
X
X
NA
NA
NA
D
X
X
X
X
NA
NA
NA
X
X
X
X
NA
NA
NA
E
X
X
X
X
X
X
NA
NA
NA
X
X
X
X
NA
NA
NA
F
X
X
X
X
X
X
NA
NA
NA
X
X
X
X
X
X
NA
NA
NA