Intel S5500WB12V Product Specification - Page 115

Intel® Server Board S5500WB TPS Glossary Term HPA Hz I2C IA IBF ICH IC MB IFB ILM IMC INTR IP IPMB IPMI IR ITP KB KCS LAN LCD LED LPC LUN MAC MB ME MD2 MD5 ms MTTR Mux NIC NMI OBF OEM Ohm PECI PEF PEP PIA PLD PMI POST PSMI PWM Host Physical Address Definition Hertz (1 cycle / second) Inter-Integrated Circuit Bus Intel® Architecture Input Buffer I/O Controller Hub Intelligent Chassis Management Bus I/O and Firmware Bridge Independent Loading Mechanism Integrated Memory Controller Interrupt Internet Protocol Intelligent Platform Management Bus Intelligent Platform Management Interface Infrared In-Target Probe 1024 bytes Keyboard Controller Style Local Area Network Liquid Crystal Display Light Emitting Diode Low Pin Count Logical Unit Number Media Access Control 1024KB Management Engine Message Digest 2 - Hashing Algorithm Message Digest 5 - Hashing Algorithm - Higher Security Milliseconds Memory Type Range Register Multiplexor Network Interface Controller Nonmaskable Interrupt Output Buffer Original Equipment Manufacturer Unit of electrical resistance Platform Environment Control Interface Platform Event Filtering Platform Event Paging Platform Information Area (This feature configures the firmware for the platform hardware) Programmable Logic Device Platform Management Interrupt Power-On Self Test Power Supply Management Interface Pulse-Width Modulation Revision 1.9 101 Intel order number E53971-008