Intel S5500WB12V Product Specification - Page 35

Intel, QuickPath Memory Controller

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Intel® Server Board S5500WB TPS Functional Architecture In the current implementation, Intel® QPI ports are capable of operating at transfer rates of up to 6.4 GT/s. Intel® QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, and quarter - 5 lanes) independently in each direction between a pair of devices communicating via the Intel® QPI. The server boards support full-width communication only. For more information see the Intel® QPI Overview Rev 1.04 (Document#: 380531) 3.4 Intel® QuickPath Memory Controller The Intel® 5500 series and 5600 series processors have an integrated memory controller on its package. Each processor produces up to three channels of DDR3 memory. The Intel® QPI Memory Controller supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies. The memory controller supports both Registered DIMMs (RDIMMs) and Unbuffered DIMMs (UDIMMs). Mixing of RDIMMs and UDIMMs is not supported. 3.4.1 Supported Memory The Intel® Server Board S5500WB supports six DDR3 memory channels (three per processor socket) with two DIMMs on the first channel and one DIMM on the second and third channels of each processor. Therefore, the server board supports up to 8 DIMMs with dual-processor sockets with a maximum memory capacity of 128 GB. The server board supports DDR3 800, DDR3 1067, and DDR3 1333 memory technologies. Memory modules of mixed speed are supported by automatic selection of the highest common frequency of all memory modules. The following configurations are not supported, validated or recommended:  Mixing of RDIMMs and UDIMMs is not supported  Mixing of memory type, size, speed and/or rank has not been validated and is not supported  Mixing memory vendors has not been validated and is not recommended  Non-ECC memory has not been validated and is not supported in a server environment Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not recommended for use in a server environment The Intel® Server Board S5500WB uses a 2:1:1 memory DIMM layout. A 2:1:1 layout was chosen for its lowest power for a particular bandwidth and because it allows the maximum possible bandwidth when a 1:1:1 memory population is used. 3.4.2 Memory Subsystem Nomenclature DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets. Revision 1.9 21 Intel order number E53971-008

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Intel® Server Board S5500WB TPS
Functional Architecture
Revision 1.9
Intel order number E53971-008
21
In the current implementation, Intel
®
QPI ports are capable of operating at transfer rates of up to
6.4 GT/s. Intel
®
QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, and
quarter - 5 lanes) independently in each direction between a pair of devices communicating via
the Intel
®
QPI. The server boards support full-width communication only.
For more information see the
Intel
®
QPI Overview Rev 1.04
(Document#: 380531)
3.4
Intel
®
QuickPath Memory Controller
The Intel
®
5500 series and 5600 series processors have an integrated memory controller on its
package. Each processor produces up to three channels of DDR3 memory. The Intel
®
QPI
Memory Controller supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies.
The memory controller supports both Registered DIMMs (RDIMMs) and Unbuffered DIMMs
(UDIMMs).
Mixing of RDIMMs and UDIMMs is not supported.
3.4.1
Supported Memory
The Intel
®
Server Board S5500WB supports six DDR3 memory channels (three per processor
socket) with two DIMMs on the first channel and one DIMM on the second and third channels of
each processor. Therefore, the server board supports up to 8 DIMMs with dual-processor
sockets with a maximum memory capacity of 128 GB.
The server board supports DDR3 800, DDR3 1067, and DDR3 1333 memory technologies.
Memory modules of mixed speed are supported by automatic selection of the highest common
frequency of all memory modules.
The following configurations are not supported, validated or recommended:
Mixing of RDIMMs and UDIMMs is not supported
Mixing of memory type, size, speed and/or rank has not been validated and is
not supported
Mixing memory vendors has not been validated and is not recommended
Non-ECC memory has not been validated and is not supported in a server environment
Note
: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not
recommended for use in a server environment
The Intel
®
Server Board S5500WB uses a 2:1:1 memory DIMM layout. A 2:1:1 layout was
chosen for its lowest power for a particular bandwidth and because it allows the maximum
possible bandwidth when a 1:1:1 memory population is used.
3.4.2
Memory Subsystem Nomenclature
DIMMs are organized into physical slots on DDR3 memory channels that belong to processor
sockets.