Intel S5500WB12V Product Specification - Page 96

Errors

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Design and Environmental Specifications Intel® Server Board S5500WB TPS 9.4 Errors This section outlines how errors are routed in the hardware to ensure appropriate FW action (logging, fan control, system management, and so forth) is taken when an event occurs. 9.4.1 PROCHOT# PROCHOT# is a bi-directional signal. The CPU toggles PROCHOT# when it goes into throttling mode. The duty cycle of PROCHOT# toggling indicates the amount of throttling initiated by the CPU. FW does not monitor PROCHOT# to determine CPU throttling percentage. Instead, it obtains outbound CPU throttling data via PECI. The path between the CPU's and IBMC (TTL_CPU_PROCHOT#) is there as a backup. An external source can also toggle PROCHOT# to force the CPU to go into throttling mode. This usually happens when the system reaches a certain thermal threshold. VRHOT is an output of the CPU VR controller, which is capable of throttling the CPU via PROCHOT#. Some simple masking circuitry is required to prevent the VRHOT from asserting the PROCHOT# to the CPUs at the time of CPU_RST#. This keeps the VRHOT from unintentionally causing the CPU to disable. FW monitors VRHOT and creates a SEL event if VRHOT is asserted. There is no fan action as a result of the BMC seeing VRHOT. 9.4.2 THERMTRIP# THERMTRIP# comes from the CPU. The THERMTRIP# signal is tied to a unique GPI on IBMC for FW to monitor. The combined THERMTRIP#'s from both CPUs is also tied to the ICH10R THERMTRIP input to cause an automatic Power Off condition when activated. 9.4.3 CATERR# The CATERR# signal from the CPU signals a catastrophic error occurred. CATERR# may signal two types of issues. One type is a warning and is indicated by a pulse on the signal. The other is the static critical error, which is indicated by a continuously asserted level on the signal. The BMC only logs the static Critical Error events and ignores the warnings indicated by the pulse. An error on the CPU is immediately communicated to the ICH10R for notification. 82 Revision 1.9 Intel order number E53971-008

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Design and Environmental Specifications
Intel® Server Board S5500WB TPS
Revision 1.9
Intel order number E53971-008
82
9.4
Errors
This section outlines how errors are routed in the hardware to ensure appropriate FW action
(logging, fan control, system management, and so forth) is taken when an event occurs.
9.4.1
PROCHOT#
PROCHOT# is a bi-directional signal. The CPU toggles PROCHOT# when it goes into throttling
mode. The duty cycle of PROCHOT# toggling indicates the amount of throttling initiated by the
CPU. FW does not monitor PROCHOT# to determine CPU throttling percentage. Instead, it
obtains outbound CPU throttling data via PECI. The path between the CPU’s and IBMC
(TTL_CPU_PROCHOT#) is there as a backup.
An external source can also toggle PROCHOT# to force the CPU to go into throttling mode.
This usually happens when the system reaches a certain thermal threshold. VRHOT is an
output of the CPU VR controller, which is capable of throttling the CPU via PROCHOT#. Some
simple masking circuitry is required to prevent the VRHOT from asserting the PROCHOT# to
the CPUs at the time of CPU_RST#. This keeps the VRHOT from unintentionally causing the
CPU to disable. FW monitors VRHOT and creates a SEL event if VRHOT is asserted. There is
no fan action as a result of the BMC seeing VRHOT.
9.4.2
THERMTRIP#
THERMTRIP# comes from the CPU. The THERMTRIP# signal is tied to a unique GPI on IBMC
for FW to monitor. The combined THERMTRIP#
’s from both CPUs
is also tied to the ICH10R
THERMTRIP input to cause an automatic Power Off condition when activated.
9.4.3
CATERR#
The CATERR# signal from the CPU signals a catastrophic error occurred. CATERR# may
signal two types of issues. One type is a warning and is indicated by a pulse on the signal. The
other is the static critical error, which is indicated by a continuously asserted level on the signal.
The BMC only logs the static Critical Error events and ignores the warnings indicated by the
pulse. An error on the CPU is immediately communicated to the ICH10R for notification.