AMD AMD-K6-2/450 Design Guide - Page 20
States after RESET and INIT
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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide States after RESET and INIT 23913A/0-November 2000 Register States after RESET and INIT After the processor has completed its initialization following the recognition of an asserted RESET or INIT signal, the states of all architecture registers and MSRs are compatible with those of Pentium processors. Differences are listed in Table 2 through Table 4. Table 2. AMD-K6™E Processor (Model 7) and AMD-K6™ Processor (Model 8/[7:0]) State after RESET Register EDX EFER STAR2 WHCR RESET State 0000_05MSh1 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h Notes: 1. "M" represents the Model and "S" represents the Stepping. 2. Processor Model 7 does not support the STAR register. Table 3. AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E Processor (Model 8/[F:8]) State after RESET Register EDX EFER PFIR PSOR STAR UWCCR WHCR RESET State 0000_05MSh1 0000_0000_0000_0002h 0000_0000_0000_0000h 0000_0000_0000_01SBh1,2 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h Notes: 1. "M" represents the Model and "S" represents the Stepping. 2. "B" represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of RESET. 8 States after RESET and INIT