AMD AMD-K6-2/450 Design Guide - Page 48

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Page Flush/Invalidate Register (PFIR) Models 8/[F:8], 9, and D contain the Page Flush/Invalidate Register (PFIR) (see Figure 9) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space. The total amount of L1 cache in the processor is 64 Kbytes. Using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache. When the PFIR is written to (using the WRMSR instruction), the invalidation and, optionally, the flushing begins. The PFIR register is MSR C000_0088h. Note: The invalidate and flush operations affect both the L1 and L2 caches on models 9 and D. 63 32 31 12 11 9 8 7 10 LINPAGE P F F / I Symbol LINPAGE PF F/I Reserved Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command Bit 31-12 8 0 Figure 9. Page Flush/Invalidate Register (PFIR) (Models 8/[F:8], 9, and D) LINPAGE Field This 20-bit field must be written with bits 31:12 of the linear address of the 4-Kbyte page that is to be invalidated and optionally flushed from the L1 cache. PF Bit If an attempt to invalidate or flush a page results in a page fault, the processor sets the PF bit to 1, and the invalidate or flush operation is not performed (even though invalidate operations do not normally generate page faults). In this case, an actual page fault exception is not generated. If the PF bit equals 0 after an invalidate or flush operation, then the operation executed successfully. The PF bit must be read after every write to the PFIR register to determine if the invalidate or flush operation executed successfully. 36 Model 8/[F:8] Registers