AMD AMD-K6-2/450 Design Guide - Page 43

23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Symbol Description Bits UC1 Uncacheable Memory Type 32 WC1 Write-Combining Memory Type 33 Symbol Description Bits UC0 Uncacheable Memory Type 0 WC0 Write-Combining Memory Type 1 63 49 48 34 33 32 31 17 16 2 10 Physical Base Address 1 WU Physical Address Mask 1 C C 11 Physical Base Address 0 WU Physical Address Mask 0 C C 00 MTRR1 MTRR0 Figure 7. UC/WC Cacheability Control Register (UWCCR) (Models 8/[F:8], 9, and D) Physical Base Address n (n=0, 1) This address is the 15 most-significant bits of the physical base address of the memory range. The least-significant 17 bits of the base address are not needed because the base address is by definition always aligned on a 128-Kbyte boundary. Physical Address Mask n (n=0, 1) This value is the 15 most-significant bits of a physical address mask that is used to define the size of the memory range. This mask is logically ANDed with both the physical base address field of the UWCCR register and the physical address generated by the processor. If the results of the two AND operations are equal, then the generated physical address is considered within the range. That is, if: Mask & Physical Base Address = Mask & Physical Address Generated then, the physical address generated by the processor is in the range. WCn (n=0, 1) When set to 1, this memory range is defined as writecombinable (refer to Table 15). Write-combinable memory is uncacheable. UCn (n=0, 1) When set to 1, this memory range is defined as uncacheable (refer to Table 15). Table 15. WC/UC Memory Type for UWCCR Register WCn 0 1 0 or 1 UCn Memory Type 0 No effect on cacheability or write-combining 0 Write-combining memory range (uncacheable) 1 Uncacheable memory range Model 8/[F:8] Registers 31