AMD AMD-K6-2/450 Design Guide - Page 36

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Extended Feature Enable Register (EFER) The Extended Feature Enable Register (EFER) contains the control bits that enable the extended features of the processor. Figure 5 shows the format of the EFER register, and Table 13 defines the function of each bit of the EFER register. The EFER register is MSR C000_0080h. Note: The EFER register as defined in models 7 and 8/[7:0] is defined differently in Model 8/[F:8]. A complete description of the newly defined register is included in this section for Model 8/[F:8]. 63 43 210 DS EWBEC P C EE Reserved Symbol Description Bit EWBEC EWBE Control 3-2 DPE Data Prefetch Enable 1 SCE System Call Extension 0 Figure 5. Extended Feature Enable Register (EFER) (Model 8/[F:8]) Table 13. Extended Feature Enable Register (EFER) Definition (Model 8/[F:8]) Bit Description 63-4 Reserved 3-2 EWBE# Control (EWBEC) 1 Data Prefetch Enable (DPE) 0 System Call Extension (SCE) R/W Function R Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. This 2-bit field controls the behavior of the processor with R/W respect to the ordering of write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE# Disable (GEWBED) and Speculative EWBE Disable (SEWBED), respectively. DPE must be set to 1 to enable data prefetching (this is the default setting following reset). If enabled, cache misses initiR/W ated by a memory read within a 32-byte cache line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. External Write Buffer Empty Control Field Model 8/[F:8] contains an 8-byte write merge buffer that allows the processor to conditionally combine data from multiple noncacheable write cycles into this merge buffer. The merge 24 Model 8/[F:8] Registers