AMD AMD-K6-2/450 Design Guide - Page 62
L2 Tag or Data Location AMD-K6™-2E+ Processor-EDX, L2 Tag or Data Location AMD-K6™
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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20 19 18 17 16 15 14 T / Way Set D Reserved Symbol Description Bit Set Selects the desired cache set 14-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 6 5 4 32 1 0 L D i n e Octet w o r d Figure 20. L2 Tag or Data Location (AMD-K6™-2E+ Processor)-EDX Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20 19 18 17 16 15 6 5 4 32 1 0 T / Way D L D Set i n e Octet w o r d Reserved Symbol Description Bit Set Selects the desired cache set 15-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 Figure 21. L2 Tag or Data Location (AMD-K6™-IIIE+ Processor)-EDX 50 Model D Registers