AMD AMD-K6-2/450 Design Guide - Page 3

Contents, Preliminary Information - cpu

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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Contents Contents Revision History xi Introduction 1 Audience 1 Processor Models and Steppings 2 AMD-K6™E Embedded Processor 3 AMD-K6™-2 Processor 3 AMD-K6™-2E Embedded Processor 4 AMD-K6™-2E+ Embedded Processor 4 AMD-K6™-III Processor 5 AMD-K6™-IIIE+ Embedded Processor 5 BIOS Consideration Checklist 6 CPUID 6 CPU Speed Detection 6 Model-Specific Registers (MSRs 6 Cache Testing 7 SMM Issues 7 States after RESET and INIT 8 Register States after RESET and INIT 8 Processor State after INIT 9 Built-In Self-Test (BIST 10 CPUID Identification Algorithms 11 System Management Mode (SMM 13 State-Save Map Differences 13 I/O Trap Dword Differences 13 Model-Specific Registers Overview 14 Standard Model-Specific Registers (All Models 16 Model 7 and Model 8/[7:0] Registers 17 Extended Feature Enable Register (EFER 18 Write Handling Control Register (WHCR 19 SYSCALL/SYSRET Target Address Register (STAR 22 iii

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Contents
iii
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Processor Models and Steppings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
AMD-K6™E Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . 3
AMD-K6™-2 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
AMD-K6™-2E Embedded Processor. . . . . . . . . . . . . . . . . . . . . . 4
AMD-K6™-2E+ Embedded Processor. . . . . . . . . . . . . . . . . . . . . 4
AMD-K6™-III Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AMD-K6™-IIIE+ Embedded Processor . . . . . . . . . . . . . . . . . . . 5
BIOS Consideration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPU Speed Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . . 6
Cache Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SMM Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
States after RESET and INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register States after RESET and INIT . . . . . . . . . . . . . . . . . . . 8
Processor State after INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPUID Identification Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
State-Save Map Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Trap Dword Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Model-Specific Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standard Model-Specific Registers (All Models) . . . . . . . . . . 16
Model 7 and Model 8/[7:0] Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 18
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 19
SYSCALL/SYSRET Target Address Register (STAR) . . . . . . 22