AMD AMD-K6-2/450 Design Guide - Page 46

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Processor State Observability Register (PSOR) Models 8/[F:8], 9, and standard-power versions of Model D provide the Processor State Observability Register (PSOR) as defined in Figure 8. The PSOR register is MSR C000_0087h. Note: See page 46 for definitions of the PSOR bit fields for lowpower Model D processors. . 63 9 87 432 0 N O L STEP BF 2 Reserved Symbol Description Bit NOL2 No L2 Functionality 8 STEP Processor Stepping 7-4 BF Bus Frequency Divisor 2-0 Figure 8. Processor State Observability Register (PSOR) (Models 8/[F:8], 9, and Standard-Power D) NOL2 Bit This read-only bit indicates whether the processor contains an L2 cache. Note: This bit is always set to 1 for Model 8/[F:8]. Note: This bit is always set to 0 for Models 9 and D. STEP Field This read-only field contains the stepping ID. This is identical to the value returned by the CPUID standard function 1 in EAX[3:0]. BF Field This read-only field contains the value of the BF signals sampled by the processor during the falling transition of RESET, which allows the BIOS to determine the frequency of the host bus. s The core frequency must first be known, which can be determined using the Time Stamp Counter method (See "Time Stamp Counter (TSC)" on page 16). s The core frequency is then divided by the processor-clock to bus-clock ratio as determined by the BF field of the PSOR register (see Table 17 and Table 18 on page 35). s The result is the frequency of the processor bus. 34 Model 8/[F:8] Registers