AMD AMD-K6-2/450 Design Guide - Page 9
List of Tables - iii
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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide List of Tables List of Tables Table 1. Features of the AMD-K6™ Processor Family 2 Table 2. AMD-K6™E Processor (Model 7) and AMD-K6™ Processor (Model 8/[7:0]) State after RESET 8 Table 3. AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E Processor (Model 8/[F:8]) State after RESET 8 Table 4. AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and AMD-K6™-IIIE+ Processors (Model D) State after RESET 9 Table 5. Recommended Boot Strings for AMD-K6™ Processors . 11 Table 6. AMD-K6™ Processor I/O Trap Dword Configuration at Offset FFA4h 13 Table 7. Summary by Register of MSR Differences within the AMD-K6™ Family 14 Table 8. Summary by Model of MSR Differences within the AMD-K6™ Family 15 Table 9. Model-Specific Registers Supported by Models 7 and 8/[7:0 17 Table 10. Extended Feature Enable Register (EFER) Definition (Models 7 and 8/[7:0 18 Table 11. SYSCALL/SYSRET Target Address Register (STAR) Definition (Models 8, 9, and D 22 Table 12. Model-Specific Registers Supported by Model 8/[F:8] . . 23 Table 13. Extended Feature Enable Register (EFER) Definition (Model 8/[F:8 24 Table 14. Write Ordering and Performance Settings for EFER Register 26 Table 15. WC/UC Memory Type for UWCCR Register 31 Table 16. Valid Masks and Range Sizes for UWCCR Register. . . . 32 Table 17. Processor-to-Bus Clock Ratios (Models 8/[F:8] and 9) . . 35 ix