Home » AMD Manuals » Processors » AMD AMD-K6-2/450 » Manual Viewer

AMD AMD-K6-2/450 Design Guide - Page 57

Model D Registers

Add to My Manuals
Save this manual to your list of manuals

Page 57 highlights

23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Model D Registers The AMD-K6-2E+ and AMD-K6-IIIE+ processors (Model D) provide the twelve model-specific registers listed in Table 22. The contents of ECX selects the MSR to be addressed by the RDMSR and WRMSR instruction. The AMD-K6-2E+ and AMD-K6-IIIE+ processors contain a split Level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. In addition, these processors also contain a 128Kbyte (AMD-K6-2E+ processor) or a 256-Kbyte (AMD-K6-IIIE+ processor), 4-way set associative, unified Level-2 (L2) cache. Further performance gains are achieved by the implementation of a write allocation scheme. Table 22. Model-Specific Registers Supported by Model D Register Name Mnemonic ECX Value Description Comments Machine-Check Address Register MCAR 00h page 16 Identical on all models Machine-Check Type Register MCTR 01h page 16 Identical on all models Test Register 12 TR12 0Eh page 16 Identical on all models Time Stamp Counter TSC 10h page 16 Identical on all models Extended Feature Enable Register EFER C000_0080h page 39 Adds L2 Disable bit (L2D) to Model 8/[F:8] implementation Write Handling Control Register WHCR C000_0082h page 27 Identical to Model 8/[F:8] SYSCALL/SYSRET Target Address Register STAR C000_0081h page 22 Identical to Model 8/[7:0] UC/WC Cacheability Control Register UWCCR C000_0085h page 30 Identical to Model 8/[F:8] Processor State Observability Register PSOR C000_0087h page 341, page 462 Standard-power implementation is identical to Model 8/[F:8]. Lowpower implementation adds new fields and renames BF to EBF. Page Flush/Invalidate Register PFIR C000_0088h page 36 Identical to Model 8/[F:8] Level-2 Cache Array Access Register L2AAR C000_0089h page 48 Identical to Model 9, but note differing L2 cache sizes on Model D. Enhanced Power Management Register2 EPMR C000_0086h page 54 New for Model D. Supported on low-power versions only. Notes: 1. Standard-power versions only. 2. Low-power versions only. Model D Registers 45

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
Introduction	13
Audience	13
Processor Models and Steppings	14
AMDK6™E Embedded Processor	15
Model 7	15
AMDK6™2 Processor	15
Model 8/[7:0]	15
Model 8/[F:8]	15
AMDK6™2E Embedded Processor	16
Model 8/[F:8]	16
AMDK6™2E+ Embedded Processor	16
Model D/[7:4]	16
AMDK6™III Processor	17
Model 9/[3:0]	17
AMDK6™IIIE+ Embedded Processor	17
Model D/[3:0]	17
BIOS Consideration Checklist	18
CPUID	18
CPU Speed Detection	18
ModelSpecific Registers (MSRs)	18
Cache Testing	19
SMM Issues	19
States after RESET and INIT	20
Register States after RESET and INIT	20
Processor State after INIT	21
BuiltIn SelfTest (BIST)	22
CPUID Identification Algorithms	23
System Management Mode (SMM)	25
StateSave Map Differences	25
I/O Trap Dword Differences	25
ModelSpecific Registers Overview	26
Standard Model-Specific Registers (All Models)	28
MachineCheck Address Register (MCAR) and MachineCheck Type Register (MCTR)	28
Test Register 12 (TR12)	28
Time Stamp Counter (TSC)	28
Model 7 and Model 8/[7:0] Registers	29
Extended Feature Enable Register (EFER)	30
Write Handling Control Register (WHCR)	31
Write Allocation	31
Write Cacheability Detection Enable Bit	32
Write Allocate Enable Limit Field	32
Write Allocate Enable 15to16Mbyte Field.	33
SYSCALL/SYSRET Target Address Register (STAR)	34
Model 8/[F:8] Registers	35
Extended Feature Enable Register (EFER)	36
External Write Buffer Empty Control Field	36
Write Handling Control Register (WHCR)	39
Write Allocation	39
Write Allocate Enable Limit Field	40
Write Allocate Enable 15to16Mbyte Field	41
UC/WC Cacheability Control Register (UWCCR)	42
Physical Base Address n (n=0, 1)	43
Physical Address Mask n (n=0, 1)	43
WCn (n=0, 1)	43
UCn (n=0, 1)	43
Memory-Range Restrictions	44
Examples	45
Processor State Observability Register (PSOR)	46
NOL2 Bit	46
STEP Field	46
BF Field	46
Page Flush/Invalidate Register (PFIR)	48
LINPAGE Field	48
PF Bit	48
F/I Bit	49
Model 9 Registers	50
Extended Feature Enable Register (EFER)	51
Level-2 Cache Array Access Register (L2AAR)	52
LRU (Least Recently Used) Field	55
Writing to L2 Tag of AMDK6™III Processor	55
Model D Registers	57
Processor State Observability Register (PSOR) (Low-Power Versions)	58
PBF[2:0] Field	58
VID Field	58
NOL2 Bit	59
STEP Field	59
EBF[2:0] Field	59
Level-2 Cache Array Access Register (L2AAR)	60
LRU (Least Recently Used) Field	64
Writing to L2 Tag of AMDK6IIIE+ Processor	65
Enhanced Power Management Register (EPMR) (Low-Power Versions)	66
EPM 16-Byte I/O Block (Low-Power Versions Only)	67
BVC Field	67
Embedded AMD Processor Recognition	69
CPUID Instruction Overview	69
Testing for the CPUID Instruction	70
Illegal Instruction Exception Method	70
EFLAGS IDBit Method	70
Using CPUID Functions	71
Identifying the Processor’s Vendor	72
Testing For Extended Functions	73
Determining the Processor Signature	73
Identifying Supported Features	75
Determining Instruction Set Support	76
Detection Algorithm for Determining Instruction Set Support	77
CPUID Test	77
Standard Function Test	77
MMX™ Test	77
Optional SSE Test	77
Extended Functions Test	77
3DNow!™ Test	77
Vendor Check	77
3DNow! Extensions Test	78
AMD Multimedia Instruction Extensions Test	78
AMD Processor Signature (Extended Function)	78
Displaying the Processor’s Name	78
Displaying Cache Information	79
Determining AMDPowerNow!™ Technology Information	79
Sample Code	79
New AMDK6™ Processor Instructions	80
Additional Considerations	81
Software Timing Dependencies Relative to Memory Controller Setup	81
Pipelining Support	81
Read-Only Memory	82
Appendix A	83
CPUID	83
Standard Functions	84
Extended Functions	87
Cache Associativity Field Definitions	92
Associativity for L1 Caches and L1 TLBs	92
Associativity for L2 Cache	92
Appendix B	93
Values Returned by the CPUID Instruction	93

Match case Limit results 1 per page

Model D Registers

23913A/0—November 2000

Embedded AMD-K6™ Processors BIOS Design Guide

Preliminary Information

Model D Registers

The AMD-K6-2E+ and AMD-K6-IIIE+ processors (Model D)

provide the twelve model-specific registers listed in Table 22.

The contents of ECX selects the MSR to be addressed by the

RDMSR and WRMSR instruction.

The AMD-K6-2E+ and AMD-K6-IIIE+ processors contain a split

Level-1 (L1) 64-Kbyte writeback cache organized as a separate

32-Kbyte instruction cache and a 32-Kbyte data cache with

two-way set associativity. The cache line size is 32 bytes, and

lines are read from memory using an efficient pipelined burst

read cycle. In addition, these processors also contain a 128-

Kbyte (AMD-K6-2E+ processor) or a 256-Kbyte (AMD-K6-IIIE+

processor), 4-way set associative, unified Level-2 (L2) cache.

Further performance gains are achieved by the implementation

of a write allocation scheme.

Table 22.

Model-Specific Registers Supported by Model D

Mnemonic

ECX Value

Description

Comments

Machine-Check Address Register

MCAR

00h

page 16

Identical on all models

Machine-Check Type Register

MCTR

01h

page 16

Identical on all models

Test Register 12

TR12

0Eh

page 16

Identical on all models

Time Stamp Counter

TSC

10h

page 16

Identical on all models

Extended Feature Enable Register

EFER

C000_0080h

page 39

Adds L2 Disable bit (L2D) to Model

8/[F:8] implementation

Write Handling Control Register

WHCR

C000_0082h

page 27

Identical to Model 8/[F:8]

SYSCALL/SYSRET Target Address Register

STAR

C000_0081h

page 22

Identical to Model 8/[7:0]

UC/WC Cacheability Control Register

UWCCR

C000_0085h

page 30

Identical to Model 8/[F:8]

Processor State Observability Register

PSOR

C000_0087h

page 34

page 46

Notes:

Standard-power versions only.

Low-power versions only.

Standard-power implementation is

identical to Model 8/[F:8]. Low-

power implementation adds new

fields and renames BF to EBF.

Page Flush/Invalidate Register

PFIR

C000_0088h

page 36

Identical to Model 8/[F:8]

Level-2 Cache Array Access Register

L2AAR

C000_0089h

page 48

Identical to Model 9, but note dif-

fering L2 cache sizes on Model D.

Enhanced Power Management Register

EPMR

C000_0086h

page 54

New for Model D. Supported on

low-power versions only.