AMD AMD-K6-2/450 Design Guide - Page 56

L2AAR register, EAX[15] must likewise correspond to the set

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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 15:6 of the address determine the set, in which case bit 15 equal to 0 addresses sets 0 through 511, and bit 15 equal to 1 addresses sets 512 through 1023. In order to set the full 17-bit L2 tag properly when using the L2AAR register, EAX[15] must likewise correspond to the set in which the tag is being written-that is, EAX[15] must be equal to EDX[15] (refer to Figure 13 on page 41 and Figure 15 on page 43). It is important to note that this special consideration is only required if the AMD-K6-III processor will subsequently be expected to properly execute instructions or access data from the L2 cache following the setup of the L2 cache by means of the L2AAR register. If the intent of using the L2AAR register is solely to test or debug the L2 cache without the subsequent intent of executing instructions or accessing data from the L2 cache, then this consideration is not required. 44 Model 9 Registers

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44
Model 9 Registers
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
15:6 of the address determine the set, in which case bit 15 equal
to 0 addresses sets 0 through 511, and bit 15 equal to 1
addresses sets 512 through 1023.
In order to set the full 17-bit L2 tag properly when using the
L2AAR register, EAX[15] must likewise correspond to the set in
which the tag is being written—that is, EAX[15] must be equal
to EDX[15] (refer to Figure 13 on page 41 and Figure 15 on
page 43).
It is important to note that this special consideration is only
required if the AMD-K6-III processor will subsequently be
expected to properly execute instructions or access data from
the L2 cache following the setup of the L2 cache by means of
the L2AAR register. If the intent of using the L2AAR register is
solely to test or debug the L2 cache without the subsequent
intent of executing instructions or accessing data from the L2
cache, then this consideration is not required.