AMD AMD-K6-2/450 Design Guide - Page 4

Preliminary Information, Embedded AMD-K6™ Processors BIOS Design Guide

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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Model 8/[F:8] Registers 23 Extended Feature Enable Register (EFER 24 Write Handling Control Register (WHCR 27 UC/WC Cacheability Control Register (UWCCR 30 Processor State Observability Register (PSOR 34 Page Flush/Invalidate Register (PFIR 36 Model 9 Registers 38 Extended Feature Enable Register (EFER 39 Level-2 Cache Array Access Register (L2AAR 40 Model D Registers 45 Processor State Observability Register (PSOR) (Low-Power Versions 46 Level-2 Cache Array Access Register (L2AAR 48 Enhanced Power Management Register (EPMR) (Low-Power Versions 54 EPM 16-Byte I/O Block (Low-Power Versions Only 55 Embedded AMD Processor Recognition 57 CPUID Instruction Overview 57 Testing for the CPUID Instruction 58 Using CPUID Functions 59 Identifying the Processor's Vendor 60 Testing For Extended Functions 61 Determining the Processor Signature 61 Identifying Supported Features 63 Determining Instruction Set Support 64 Detection Algorithm for Determining Instruction Set Support 65 AMD Processor Signature (Extended Function 66 Displaying the Processor's Name 66 Displaying Cache Information 67 Determining AMD PowerNow!™ Technology Information . . 67 Sample Code 67 New AMD-K6™ Processor Instructions 68 Additional Considerations 69 iv Contents

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iv
Contents
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Model 8/[F:8] Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 24
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 27
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . 30
Processor State Observability Register (PSOR) . . . . . . . . . . . 34
Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 36
Model 9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 39
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . . 40
Model D Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Processor State Observability Register (PSOR)
(Low-Power Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . . 48
Enhanced Power Management Register (EPMR)
(Low-Power Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
EPM 16-Byte I/O Block (Low-Power Versions Only). . . . . . . . 55
Embedded AMD Processor Recognition. . . . . . . . . . . . . . . . . . . . . . . 57
CPUID Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Testing for the CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . 58
Using CPUID Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I
dentifying the Processor’s Vendor . . . . . . . . . . . . . . . . . . . . . 60
Testing For Extended Functions . . . . . . . . . . . . . . . . . . . . . . . 61
Determining the Processor Signature . . . . . . . . . . . . . . . . . . . 61
Identifying Supported Features . . . . . . . . . . . . . . . . . . . . . . . . 63
Determining Instruction Set Support. . . . . . . . . . . . . . . . . . . . 64
Detection Algorithm for Determining Instruction Set
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AMD Processor Signature (Extended Function). . . . . . . . . . . 66
Displaying the Processor’s Name . . . . . . . . . . . . . . . . . . . . . . . 66
Displaying Cache Information . . . . . . . . . . . . . . . . . . . . . . . . . 67
Determining AMD PowerNow!™ Technology Information . . 67
Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
New AMD-K6™ Processor Instructions. . . . . . . . . . . . . . . . . . . . . . . . 68
Additional Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69