AMD AMD-K6-2/450 Design Guide - Page 53
L2 Cache Sector and Line Organization, L2 Tag or Data Location AMD-K6™, Processor-EDX
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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Octet 0 Octet 1 Octet 2 Octet 3 Upper Dword Lower Dword Upper Dword Lower Dword Line 1 Line 0 Sector Figure 12. L2 Cache Sector and Line Organization Bit 20 of EDX (T/D) determines whether the access is to the L2 cache data or tag. Table 21 on page 42 describes the operation that is performed based on the instruction and the T/D bit. Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20 19 18 17 16 15 6 5 4 32 1 0 T / Way D L D Set i n e Octet w o r d Reserved Symbol Description Bit Set Selects the desired cache set 15-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 Figure 13. L2 Tag or Data Location (AMD-K6™-III Processor)-EDX Model 9 Registers 41