AMD AMD-K6-2/450 Design Guide - Page 64

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 31 Tag 14 13 12 11 10 9 8 7 Line1ST Line0ST 0 C LRU M D Reserved Symbol Description Bit Tag Tag data read or written 31-14 Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10 Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8 LRU Two bits of LRU for each way 7-0 Figure 23. L2 Tag Information (AMD-K6™-2E+ Processor)-EAX 31 15 14 12 11 10 9 8 7 Tag Line1ST Line0ST 0 C LRU M D Reserved Symbol Description Bit Tag Tag data read or written 31-15 Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10 Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8 LRU Two bits of LRU for each way 7-0 Figure 24. L2 Tag Information (AMD-K6™-IIIE+ Processor)-EAX LRU (Least Recently Used) Field For the 4-way set associative L2 cache, each way has a 2-bit LRU field for each sector. Values for the LRU field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is "most recently used," and 11b indicates that the sector is "least recently used" (see Figure 25 on page 53). EAX[7:6] indicate the LRU information for Way 0, EAX[5:4] for Way 1, EAX[3:2] for Way 2, and EAX[1:0] for Way 3. 52 Model D Registers