Intel BX80580Q9400 User Manual - Page 32

Processor Voltage Regulators, Front-Side Bus FSB, Processor Power Management, Processor Active

Get Intel BX80580Q9400 - Core 2 Quad 2.66 GHz Processor PDF manuals and user guides
UPC - 735858203074
View all Intel BX80580Q9400 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 32 highlights

Development Board Features 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 Processor Voltage Regulators The reference board implements an onboard Intel® Mobile Voltage Positioning (Intel® MVP) -6 regulator for the processor core supply. The core VR solution supports PSI2. The VR will support up to 56 amps. Slow C4 exit is supported to reduce perceptible audio noise caused by periodically exiting the C4 state. Front-Side Bus (FSB) The Front Side Bus (FSB) on the development board supports data rates of 800 MT/s (200-MHz quad pumped, FSB-800) & 1067 MT/s (266-MHz quad pumped, FSB-1067). The FSB is AGTL+ and will be running at 1.05 V. Processor Power Management Intel® Core™ 2 Duo processor SL9400 and SU9400 supports C0-C6 power states. This processor also supports C2E and C4E. Additionally, the processor supports a new processor state, Intel Deep Power Down Technology, that brings the CPU leakage power down to the lowest possible. DPWR# protocol is also supported on the development board through signal H_DPWR#. Processor Active Cooling The system supports PWM based FAN speed control. Fan circuitry is controlled by the signal CPU_PWM_FAN signal from the EC (PWM signal from the H8 is driven high to 3.3 V and low to 0 V at about 40 kHz carrier frequency). A 3-pin header J2B3 is provided to support FAN Tacho output measurement for the CPU. Manual Processor Voltage ID (VID) Support The development board supports manual VID operation for processor VR. A jumper J2B2 is provided to incorporate "VID override" to allow the overriding of CPU VID outputs to the CPU VCC Core VR. The intent of this "VID override' circuit is for ease of debug and testing. 32 Development Kit User's Manual

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
Development Board Features
32
Development Kit User’s Manual
3.6.2
Processor Voltage Regulators
The reference board implements an onboard Intel® Mobile Voltage Positioning (Intel®
MVP) -6 regulator for the processor core supply. The core VR solution supports PSI2.
The VR will support up to 56 amps. Slow C4 exit is supported to reduce perceptible
audio noise caused by periodically exiting the C4 state.
3.6.3
Front-Side Bus (FSB)
The Front Side Bus (FSB) on the development board supports data rates of 800 MT/s
(200-MHz quad pumped, FSB-800) & 1067 MT/s (266-MHz quad pumped, FSB-1067).
The FSB is AGTL+ and will be running at 1.05 V.
3.6.4
Processor Power Management
Intel® Core™ 2 Duo processor SL9400 and SU9400 supports C0-C6 power states. This
processor also supports C2E and C4E. Additionally, the processor supports a new
processor state, Intel Deep Power Down Technology, that brings the CPU leakage
power down to the lowest possible.
DPWR# protocol is also supported on the
development board through signal H_DPWR#.
3.6.5
Processor Active Cooling
The system supports PWM based FAN speed control. Fan circuitry is controlled by the
signal CPU_PWM_FAN signal from the EC (PWM signal from the H8 is driven high to
3.3 V and low to 0 V at about 40 kHz carrier frequency).
A 3-pin header J2B3 is provided to support FAN Tacho output measurement for the
CPU.
3.6.6
Manual Processor Voltage ID (VID) Support
The development board supports manual VID operation for processor VR. A jumper
J2B2 is provided to incorporate “VID override” to allow the overriding of CPU VID
outputs to the CPU VCC Core VR. The intent of this “VID override’ circuit is for ease of
debug and testing.