Intel S1200BT Technical Product Specification - Page 33

Intel® Server Board S1200BT TPS Functional Architecture  For Intel® Xeon® E3-1200 Processors or the 2nd Generation Intel® Core™ i3 Processors, the DIMM speeds of 1066 or 1333 MT/s (megatransfers/second).  For Intel® Xeon® E3-1200 V2 Processors or the 3rd Generation Intel® Core™ i3 Processors, the DIMM speeds of 1333/1600 MT/s (megatransfers/second).  Only Unregistered (Unbuffered) DIMMs (UDIMMs) are supported  Only Error Correction Code (ECC) enabled DIMMs are supported  UDIMMs may or may not have thermal sensors Note: UDIMMs must be ECC, and may or may not have thermal sensors. S1200BT BIOS has the following limitations:  No support for LV DIMMs  No support for RDIMMs  All channels in a system will run at the fastest common frequency  Mixing ECC and non-ECC UDIMMs anywhere on the platform is not supported  Static Closed Loop Thermal Throttling (CLTT) supported through BMC (requires ECC DIMMs with thermal sensor) 3.2.2 Post Error Codes The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST, this same range of POST code values is used for reporting other system errors.  0xE8 - No Usable Memory Error: If no usable memory is available, the BIOS emits a beep code and displays POST Diagnostic LED code 0xE8 and halts the system. This can also occur if all memory in the system fails and/or has become disabled during memory initialization. For example, if a DDR3 DIMM has no SPD information, the BIOS treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the only DDR3 DIMM installed in the system, there is no usable memory, and the BIOS goes to a memory error code 0xE8 as described above.  0x53/0x55/0XE8 - DIMM SPD does not respond or DIMM SPD Read Error, the DIMM will not be detected, if the SPD deos not respond, which could result in "No memory Installed" or "No Usable Memory" Memory Error Halt 0X53, 0x55, or 0xE8, or could result later in an invalid configuration if the "no SPD" DIMM is in Slot 1 on the channel..  0x51 - Memory SPD Error: If the DIMM does respond but the SPD cannot be successfully read, that would cause a "Memory SPD Error", memory error halt 0X51. For each memory channel, once the DIMM SPD parameters have been read, they are checked to verify that the DIMMs on the channel are a valid configuration, DIMM speed and size, ECC capability, and in which memory sholts the DIMMs are installed. An invalid configuration will cause the system to halt..  0xEA - Channel Training Error: If the memory initialization process is unable to properly perform the Data/Data Strobe timing training on a memory channel, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during the beeping. If there is usable memory in the system on other channels, POST memory initialization continues. Otherwise, the system beeps and halts with POST Diagnostic LED code 0xEA staying displayed. Revision 2.0 21 Intel order number G13326-004