Intel S1200BT Technical Product Specification - Page 83

Intel SMX Safer Mode Extensions

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Intel® Server Board S1200BT TPS BIOS User Interface Note: Modifying this setting may affect performance. Comments: MLC Streamer is normally Enabled for the best efficiency in L2 Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. For more information. 21. MLC Spatial Prefetcher Option Values: Enabled Disabled Help Text: [Enabled] - Fetches adjacent cache line (128 bytes) when required data is not currently in cache. [Disabled] - Only fetches cache line with data required by the processor (64 bytes). Comments: MLC Spatial Prefetcher is normally Enabled, for best efficiency in L2 Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. For more information 22. DCU Data Prefetcher Option Values: Enabled Disabled Help Text: The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. [Disabled] - Only fetches cache line with data required by the processor (64 bytes). Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Data Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. For more information. 23. DCU Instruction Prefetcher Option Values: Enabled Disabled Help Text: The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. [Disabled] - Only fetches cache line with data required by the processor (64 bytes). Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 I Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. For more information. 24. Intel (SMX) Safer Mode Extensions Revision 2.0 71 Intel order number G13326-004

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Intel®
Server Board S1200BT TPS
BIOS User Interface
Revision 2.0
Intel order number G13326-004
71
Note:
Modifying this setting may affect performance.
Comments:
MLC Streamer is normally Enabled for the best efficiency in L2 Cache
and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks. For more information.
21.
MLC Spatial Prefetcher
Option Values:
Enabled
Disabled
Help Text:
[Enabled]
–
Fetches adjacent cache line (128 bytes) when required data is not
currently in cache.
[Disabled] - Only fetches cache line with data required by the processor (64
bytes).
Comments:
MLC Spatial Prefetcher is normally
Enabled
, for best efficiency in L2
Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks. For more information
22.
DCU Data Prefetcher
Option Values:
Enabled
Disabled
Help Text:
The next cache line will be prefetched into L1 data cache from L2 or system
memory during unused cycles if it sees that the processor core has accessed
several bytes sequentially in a cache line as data.
[Disabled]
–
Only fetches cache line with data required by the processor (64
bytes).
Comments:
DCU Data Prefetcher is normally
Enabled
, for best efficiency in L1 Data
Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks. For more information.
23.
DCU Instruction Prefetcher
Option Values:
Enabled
Disabled
Help Text:
The next cache line will be prefetched into L1 instruction cache from L2 or
system memory during unused cycles if it sees that the processor core has
accessed several bytes sequentially in a cache line as data. [Disabled]
–
Only
fetches cache line with data required by the processor (64 bytes).
Comments:
DCU Data Prefetcher is normally
Enabled
, for best efficiency in L1 I
Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks. For more information.
24.
Intel (SMX) Safer Mode Extensions