Intel S1200BT Technical Product Specification - Page 34

Memory Map and Population Rules

Page 34 highlights

Functional Architecture Intel® Server Board S1200BT TPS  0x54/0xEB - Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the same memory channel fails memory testing but usable memory remains available, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEB momentarily during the beeping, then continues POST. If all of the memory fails memory testing, then system memory error code 0xE8 (No Usable Memory) as described above.  0xED - Population Error or Invalid DIMM: If the installed memory contains an invalid DIMM configuration on any channel in the system, the system beeps and halts with POST Diagnostic LED code 0xED. The DIMM are installed incorrectly, not following the "Fill Farthest First" rule (Slot 1 must be filled before Slot 2). This will result in a DIMM Population Error, with a Memory Error Halt 0xED. Note: Mixed DIMM configurations are not supported and not validated by Intel®. 3.2.3 Memory Map and Population Rules The overall configuration is a single processor with two channels, and two DIMM slots on each channel on the Intel® Server Board S1200BT. All memory DIMMs are ECC UDIMMs only, with a maximum size of 8 GB.  Slot1 must be populated first before Slot2, on either channel.  Channel A and Channel B are independent and are not required to have the same number of DIMMs installed. Either channel may be used for a single-DIMM configuration. o When only one memory channel is populated, the memory runs in Single Channel mode, with no interleaving. o When both channels are populated identically, the memory runs in Dual Channel Symmetric mode. The memory is interleaved by full 64-byte cache lines alternating between channels, that is the first entire cache line resides in DIMM_A1, the second in DIMM_B1, and so on. This allows Adjacent Cache Line Prefetch to fetch cache lines from both channels simultaneously, approximately doubling the potential memory bandwidth. o When both channels are populated, but with different numbers of DIMMs, Intel® Flex Memory Technology divides the installed memory into two zones, using interleaved Dual Channel Symmetric mode as far as the highest address on the less-populated channel, then using uninterleaved Dual Channel Asymmetric mode for the remaining memory on the more-populated channel.  The maximum total installed memory size supported is 32 GB, using four 8 GB DIMMs.  The maximum memory bandwidth is 10.6 GB/s in Single-Channel mode or 21 GB/s in Dual-Channel Symmetric mode, assuming DDR3 running at 1333 MT/s. 22 Revision 2.0 Intel order number G13326-004

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Functional Architecture
Intel®
Server Board S1200BT TPS
Revision 2.0
Intel order number G13326-004
22
0x54/0xEB - Memory Test Error:
If a DDR3 DIMM or a set of DDR3 DIMMs on the
same memory channel fails memory testing but usable memory remains available, the
BIOS emits a beep code and displays POST Diagnostic LED code 0xEB momentarily
during the beeping, then continues POST. If all of the memory fails memory testing,
then system memory error code 0xE8 (No Usable Memory) as described above.
0xED - Population Error or Invalid DIMM:
If the installed memory contains an invalid
DIMM configuration on any channel in the system, the system beeps and halts with
POST Diagnostic LED code 0xED. The DIMM are installed incorrectly, not following the
Fill Farthest First
rule (Slot 1 must be filled before Slot 2). This will result in a DIMM
Population Error, with a Memory Error Halt 0xED.
Note:
Mixed DIMM configurations are not supported and not validated by Intel
®
.
3.2.3
Memory Map and Population Rules
The overall configuration is a single processor with two channels, and two DIMM slots on each
channel on the Intel
®
Server Board S1200BT. All memory DIMMs are ECC UDIMMs only
, with a
maximum size of 8 GB.
Slot1 must be populated first before Slot2, on either channel.
Channel A and Channel B are independent and are not required to have the same
number of DIMMs installed. Either channel may be used for a single-DIMM
configuration.
o
When only one memory channel is populated, the memory runs in Single
Channel mode, with no interleaving.
o
When both channels are populated identically, the memory runs in Dual Channel
Symmetric mode. The memory is interleaved by full 64-byte cache lines
alternating between channels, that is the first entire cache line resides in
DIMM_A1, the second in DIMM_B1, and so on. This allows Adjacent Cache Line
Prefetch to fetch cache lines from both channels simultaneously, approximately
doubling the potential memory bandwidth.
o
When both channels are populated, but with different numbers of DIMMs, Intel
®
Flex Memory Technology divides the installed memory into two zones, using
interleaved Dual Channel Symmetric mode as far as the highest address on the
less-populated channel, then using uninterleaved Dual Channel Asymmetric
mode for the remaining memory on the more-populated channel.
The maximum total installed memory size supported is 32 GB, using four 8 GB DIMMs.
The maximum memory bandwidth is 10.6 GB/s in Single-Channel mode or 21 GB/s in
Dual-Channel Symmetric mode, assuming DDR3 running at 1333 MT/s.