Intel S1200BT Technical Product Specification - Page 41

Intel®, Server Board S1200BT TPS, Functional Architecture, Revision 2.0, Intel order number G13326- - s1200bts memory support

Get Intel S1200BT PDF manuals and user guides View all Intel S1200BT manuals
Add to My Manuals
Save this manual to your list of manuals

Page 41 highlights

Intel® Server Board S1200BT TPS Functional Architecture  Interrupt controller  Multiple SPI flash interfaces  NAND/Memory interface  Sixteen mailbox registers for communication between the Integrated BMC and host  LPC ROM interface  Integrated BMC watchdog timer capability  SD/MMC card controller with DMA support  LED support with programmable blink rate controls on GPIOs  Port 80h snooping capability  Secondary Service Processor (SSP), which provides the HW capability of offloading time critical processing tasks from the main ARM core. Figure 13. Integrated BMC Hardware Revision 2.0 29 Intel order number G13326-004

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
Intel®
Server Board S1200BT TPS
Functional Architecture
Revision 2.0
Intel order number G13326-004
29
Interrupt controller
Multiple SPI flash interfaces
NAND/Memory interface
Sixteen mailbox registers for communication between the Integrated BMC and host
LPC ROM interface
Integrated BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading
time critical processing tasks from the main ARM core.
Figure 13. Integrated BMC Hardware