Intel S1200BT Technical Product Specification - Page 36

Functional Architecture Intel® Server Board S1200BT TPS To get the maximum memory size on UDIMM, you get the detailed information from following table: Table 6. UDIMM memory configuration rule for Intel® Xeon® E3-1200 V2 Processors or the 3rd Generation Intel® Core™ i3 Processors DIMM slots per channel 2 2 DIMMs populated per channel 1 2 Speed 1333,1600 1333,1600 Ranks per channel Single Rank, Dual Rank Single Rank, Dual Rank To get the maximum memory size on UDIMM, you get the detailed information from following table: Table 7. UDIMM Maximum configuration Max Memory Possible Single Rank UDIMM Dual Rank UDIMMs 1Gb DRAM Technology 4GB (4x 1GB DIMMs) 8GB (4x 2GB DIMMs) 2Gb DRAM Technology 8GB (4x 2GB DIMMs) 16GB (4x 4GB DIMMs) 4Gb DRAM Technology 16GB (4x 4GB DIMMs) 32GB (4x 8GB DIMMs) 3.2.4 Publishing System Memory For S1200 Server Boards with an SNB-DT processor, the memory configurations and population rules are relatively simple. The overall configuration is a single processor/IMC, with two channels, and two DIMM slots on each channel. All memory DIMMs are ECC UDIMMs only, with a maximum size of 8 GB.  Slot1 must be populated first before Slot2, on either channel.  Channel A and Channel B are independent and are not required to have the same number of DIMMs installed. Either channel may be used for a single-DIMM configuration. o When only one memory channel is populated, the memory runs in Single Channel mode, with no interleaving. 3.2.5 Memory RAS Support For Intel® Server Board S1200BT, the form of Memory RAS provided is Error Correction Code (ECC). ECC uses "extra bits" - 64-bit data in a 72-bit DRAM array - to add an 8-bit calculated "Hamming Code" to each 64 bits of data. This additional encoding enables the memory controller to detect and report single or double bit errors, and to correct single-bit errors. There is a specific step in memory initialization in which all of memory is cleared to zeroes before the ECC function is enabled, in order to bring the ECC codes into agreement with memory contents. During operation, in the process of every fetch from memory, the data and ECC bits are examined for each 64-bit data + 8-bit ECC group. If the ECC computation indicates that a single bit Correctable Error has occurred, it is corrected and the corrected data is passed on to the processor. If a double-bit Uncorrectable Error is detected, it cannot be corrected. In each case, a Correctable or Uncorrectable ECC Error event is generated. 24 Revision 2.0 Intel order number G13326-004