MSI KT4V User Guide - Page 63
PCI Delay Transaction, Enabled, Disabled
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BIOS Setup PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delayed transactions cycles so that transactions to and from the ISA bus are buffered and PCI bus can perform other transactions while the ISA transaction is underway. Select Enabled to support compliance with PCI specification version 2.1. Setting options: Enabled, Disabled. 3-17
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3-17
BIOS Setup
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delayed
transactions cycles so that transactions to and from the ISA bus are buffered
and PCI bus can perform other transactions while the ISA transaction is
underway.
Select
Enabled
to support compliance with PCI specification ver-
sion 2.1.
Setting options:
Enabled, Disabled
.