Asus A8R-MVP A8R-MVP User's Manual for English Edtion - Page 78

4.4.2 CPU Configuration The items in this menu show the CPU-related information that the BIOS automatically detects. Advanced BIOS SETUP UTILITY CPU Configuration Module Version: 14.08 Physical Count: 1 Logical Count: 2 AMD Athlon(tm) 64 X2 Dual Core Processor 4600+ Revision: E6 Cache L1: 128*2 KB Cache L2: 512*2 KB Speed: 2400 MHz Current FSB Multiplier: 12x Maximum FSB Multiplier: 12x Able to Change Freq: Yes uCode Patch Level: 0x4D GART Error Reporting MTRR Mapping Cool `n' Quiet HT Link Speed [Disabled] [Continuous] [Disabled] [Auto] Memory Configuration This option should remain disabled for the normal operation. The driver developer may enable it for testing purpose. Select Screen Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit v02.58 (C)Copyright 1985-2004, American Megatrends, Inc. GART Error Reporting [Disabled] Allows you to enable or disable GART error checking for testing purposes. Configuration options: [Disabled] [Enabled] MTRR Mapping [Continuous] Determines the method used for programming processor MTRRs when using more than 4 GB of system memory. Setting to [Discrete] leaves the PCI hole below the 4 GB boundary undescribed. [Continuous] explicitly describes the PCI hole as non-cacheable. Configuration options: [Continuous] [Discrete] Cool 'n' Quiet [Disabled] Enables or disables the Cool 'n' Quiet™ technology feature. Configuration options: [Enabled] [Disabled] HT Link Speed [Auto] Allows you to set the speed at which the HyperTransport link will run if the speed is lower than or equal to the system clock and if the board is capable. Configuration options: [Auto] [200 MHz] [400 MHz] [600 MHz] [800 MHz] [1 GHz] 4-22 Chapter 4: BIOS setup