Epson Apex 386/33 Canadian Product User Manual - Page 154

I/O Channel Signal Description

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Figure 6-18: Thirty-Slx Pin I/O Channels I/O Channel Signal Description The following is a description of the system board's I/O channel signals. All signal lines are TTL-compatible. I/O adapters should be designed with a maximum of two low-power Shottky(LS) loads per line. SA0 Though SA19 (I/O) Address bits 0 though 19 are used to address memory and I/O devices within the system. These 20 address lines, in addition to LA17 through LA23, allow access of up to 16Mb of memory. SA0 through SA19 are gated on the system bus when "BALE" is high and are latched on the falling edge of "BALE". These signals are generated by the microprocessor or DMA Controller. They also may be driven by other microprocessors or DMA controllers that reside on the I/O channel. Chapter 6: Appendix 35

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Figure 6-18:
Thirty-Slx Pin I/O Channels
I/O Channel Signal Description
The following is a description of the system board’s I/O channel
signals. All signal lines are TTL-compatible. I/O adapters should be
designed with a maximum of two low-power Shottky(LS) loads per line.
SA0 Though SA19 (I/O)
Address bits 0 though 19 are used to address memory and I/O devices
within the system. These 20 address lines, in addition to LA17 through
LA23, allow access of up to 16Mb of memory. SA0 through SA19 are
gated on the system bus when “BALE” is high and are latched on the
falling edge of “BALE”. These signals are generated by the
microprocessor or DMA Controller. They also may be driven by other
microprocessors or DMA controllers that reside on the I/O channel.
Chapter 6: Appendix
35